Hello, Probably I can't technically help you here, but have you considered observing the simulator behavior when similar faults happen? For example, simulate a program that access an invalid address and enable all related debug flags to track it (--debug-flags option).
Hope it helps, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-08-03 3:30 GMT+02:00 Rodolfo Guilherme Wottrich <[email protected]>: > Hello, > > I would like to request some assistance if possible. For my PhD work, I > need to be able to trigger a CPU fault when a particular condition in the > L1 cache controller is met. I am using an o3 x86 CPU and Ruby in SE mode. > > I have come to a partial solution to the problem, based on a patch I found > which dealt with a similar situation. That involves creating a new > Sequencer callback function that is used only at that specific situation in > the cache controller which triggers a sequence of actions that eventually > lead to a Fault object being instantiated in the LSQ and in the commit > stage of the pipeline. > > The problem is that although the Fault and its handling are "working" > (control flow changes and registers are updated as they should), subsequent > requests still keep being received by the cache in the mandatory queue from > the instructions following the offending one. Those instructions should > have been cancelled as in a branch misprediction and their requests should > have been removed from the LSQ to avoid inconsistency. > > Can anybody think of why I am having such a problem/how can I solve it? I > can provide specifics once the discussion starts. > > Thank you in advance. > Cheers, > > --- > Rodolfo Wottrich > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
