changeset a38c3f9c82d1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a38c3f9c82d1
description:
mem: Add a FromCache packet attribute
This patch adds a FromCache attribute to the packet, and updates a
number of the existing request commands to reflect that the request
originates from a cache. The attribute simplifies checking if a
requests came from a cache or not, and this is used by both the cache
and snoop filter in follow-on patches.
Change-Id: Ib0a7a080bbe4d6036ddd84b46fd45bc7eb41cd8f
Reviewed-by: Nikos Nikoleris <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Tony Gutierrez <[email protected]>
Reviewed-by: Steve Reinhardt <[email protected]>
diffstat:
src/mem/cache/cache.cc | 10 ++--------
src/mem/packet.cc | 34 ++++++++++++++++++++--------------
src/mem/packet.hh | 5 ++++-
3 files changed, 26 insertions(+), 23 deletions(-)
diffs (158 lines):
diff -r 55bd18998b7c -r a38c3f9c82d1 src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc Wed Aug 10 16:40:14 2016 +0100
+++ b/src/mem/cache/cache.cc Fri Aug 12 14:11:45 2016 +0100
@@ -191,14 +191,8 @@
assert(pkt->hasRespData());
pkt->setDataFromBlock(blk->data, blkSize);
- // determine if this read is from a (coherent) cache, or not
- // by looking at the command type; we could potentially add a
- // packet attribute such as 'FromCache' to make this check a
- // bit cleaner
- if (pkt->cmd == MemCmd::ReadExReq ||
- pkt->cmd == MemCmd::ReadSharedReq ||
- pkt->cmd == MemCmd::ReadCleanReq ||
- pkt->cmd == MemCmd::SCUpgradeFailReq) {
+ // determine if this read is from a (coherent) cache or not
+ if (pkt->fromCache()) {
assert(pkt->getSize() == blkSize);
// special handling for coherent block requests from
// upper-level caches
diff -r 55bd18998b7c -r a38c3f9c82d1 src/mem/packet.cc
--- a/src/mem/packet.cc Wed Aug 10 16:40:14 2016 +0100
+++ b/src/mem/packet.cc Fri Aug 12 14:11:45 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015 ARM Limited
+ * Copyright (c) 2011-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -65,6 +65,8 @@
#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4))
#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5))
#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6))
+#define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \
+ SET1(a7))
const MemCmd::CommandInfo
MemCmd::commandInfo[] =
@@ -85,20 +87,20 @@
/* WriteResp */
{ SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" },
/* WritebackDirty */
- { SET4(IsWrite, IsRequest, IsEviction, HasData),
+ { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
InvalidCmd, "WritebackDirty" },
/* WritebackClean - This allows the upstream cache to writeback a
* line to the downstream cache without it being considered
* dirty. */
- { SET4(IsWrite, IsRequest, IsEviction, HasData),
+ { SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
InvalidCmd, "WritebackClean" },
/* CleanEvict */
- { SET2(IsRequest, IsEviction), InvalidCmd, "CleanEvict" },
+ { SET3(IsRequest, IsEviction, FromCache), InvalidCmd, "CleanEvict" },
/* SoftPFReq */
{ SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
SoftPFResp, "SoftPFReq" },
/* HardPFReq */
- { SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse),
+ { SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache),
HardPFResp, "HardPFReq" },
/* SoftPFResp */
{ SET4(IsRead, IsResponse, IsSWPrefetch, HasData),
@@ -110,18 +112,19 @@
{ SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData),
WriteResp, "WriteLineReq" },
/* UpgradeReq */
- { SET5(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse),
+ { SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse,
+ FromCache),
UpgradeResp, "UpgradeReq" },
/* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */
- { SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc,
- IsRequest, NeedsResponse),
+ { SET7(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc,
+ IsRequest, NeedsResponse, FromCache),
UpgradeResp, "SCUpgradeReq" },
/* UpgradeResp */
{ SET2(IsUpgrade, IsResponse),
InvalidCmd, "UpgradeResp" },
/* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */
- { SET6(IsRead, NeedsWritable, IsInvalidate,
- IsLlsc, IsRequest, NeedsResponse),
+ { SET7(IsRead, NeedsWritable, IsInvalidate,
+ IsLlsc, IsRequest, NeedsResponse, FromCache),
UpgradeFailResp, "SCUpgradeFailReq" },
/* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC
* that it has failed, acquires line as Dirty*/
@@ -130,7 +133,8 @@
/* ReadExReq - Read issues by a cache, always cache-line aligned,
* and the response is guaranteed to be writeable (exclusive or
* even modified) */
- { SET5(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse),
+ { SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse,
+ FromCache),
ReadExResp, "ReadExReq" },
/* ReadExResp - Response matching a read exclusive, as we check
* the need for exclusive also on responses */
@@ -139,11 +143,13 @@
/* ReadCleanReq - Read issued by a cache, always cache-line
* aligned, and the response is guaranteed to not contain dirty data
* (exclusive or shared).*/
- { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadCleanReq" },
+ { SET4(IsRead, IsRequest, NeedsResponse, FromCache),
+ ReadResp, "ReadCleanReq" },
/* ReadSharedReq - Read issued by a cache, always cache-line
* aligned, response is shared, possibly exclusive, owned or even
* modified. */
- { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadSharedReq" },
+ { SET4(IsRead, IsRequest, NeedsResponse, FromCache),
+ ReadResp, "ReadSharedReq" },
/* LoadLockedReq: note that we use plain ReadResp as response, so that
* we can also use ReadRespWithInvalidate when needed */
{ SET4(IsRead, IsLlsc, IsRequest, NeedsResponse),
@@ -187,7 +193,7 @@
/* Flush Request */
{ SET3(IsRequest, IsFlush, NeedsWritable), InvalidCmd, "FlushReq" },
/* Invalidation Request */
- { SET4(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse),
+ { SET5(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse, FromCache),
InvalidateResp, "InvalidateReq" },
/* Invalidation Response */
{ SET2(IsInvalidate, IsResponse),
diff -r 55bd18998b7c -r a38c3f9c82d1 src/mem/packet.hh
--- a/src/mem/packet.hh Wed Aug 10 16:40:14 2016 +0100
+++ b/src/mem/packet.hh Fri Aug 12 14:11:45 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2015 ARM Limited
+ * Copyright (c) 2012-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -151,6 +151,7 @@
IsError, //!< Error response
IsPrint, //!< Print state matching address (for debugging)
IsFlush, //!< Flush the address from caches
+ FromCache, //!< Request originated from a caching agent
NUM_COMMAND_ATTRIBUTES
};
@@ -193,6 +194,7 @@
bool needsResponse() const { return testCmdAttrib(NeedsResponse); }
bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
bool isEviction() const { return testCmdAttrib(IsEviction); }
+ bool fromCache() const { return testCmdAttrib(FromCache); }
/**
* A writeback is an eviction that carries data.
@@ -514,6 +516,7 @@
bool needsResponse() const { return cmd.needsResponse(); }
bool isInvalidate() const { return cmd.isInvalidate(); }
bool isEviction() const { return cmd.isEviction(); }
+ bool fromCache() const { return cmd.fromCache(); }
bool isWriteback() const { return cmd.isWriteback(); }
bool hasData() const { return cmd.hasData(); }
bool hasRespData() const
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
