changeset a51ae096ca25 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a51ae096ca25
description:
commit 15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <[email protected]>
ext: update SST connector for SST 6.0
diffstat:
ext/sst/ExtMaster.cc | 2 +-
ext/sst/ExtMaster.hh | 1 -
ext/sst/ExtSlave.cc | 3 +--
ext/sst/ExtSlave.hh | 1 -
ext/sst/gem5.cc | 3 +--
ext/sst/gem5.hh | 1 -
ext/sst/libgem5.cc | 3 +--
ext/sst/tests/test6_arm_4c.py | 27 ++++++++++++++++-----------
8 files changed, 20 insertions(+), 21 deletions(-)
diffs (166 lines):
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/ExtMaster.cc
--- a/ext/sst/ExtMaster.cc Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/ExtMaster.cc Wed Aug 24 14:20:53 2016 +0100
@@ -48,7 +48,7 @@
#undef fatal
#endif
-#include <sst_config.h>
+#include <core/sst_config.h>
#include <mem/packet.hh>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/ExtMaster.hh
--- a/ext/sst/ExtMaster.hh Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/ExtMaster.hh Wed Aug 24 14:20:53 2016 +0100
@@ -48,7 +48,6 @@
#include <list>
#include <set>
-#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/elements/memHierarchy/memEvent.h>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/ExtSlave.cc
--- a/ext/sst/ExtSlave.cc Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/ExtSlave.cc Wed Aug 24 14:20:53 2016 +0100
@@ -44,8 +44,7 @@
#include "gem5.hh"
-#include <sst_config.h>
-#include <sst/core/serialization.h>
+#include <core/sst_config.h>
#include <sst/core/params.h>
#include <sst/core/output.h>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/ExtSlave.hh
--- a/ext/sst/ExtSlave.hh Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/ExtSlave.hh Wed Aug 24 14:20:53 2016 +0100
@@ -45,7 +45,6 @@
#ifndef EXT_SST_EXTSLAVE_HH
#define EXT_SST_EXTSLAVE_HH
-#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/core/output.h>
#include <sst/core/interfaces/simpleMem.h>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/gem5.cc
--- a/ext/sst/gem5.cc Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/gem5.cc Wed Aug 24 14:20:53 2016 +0100
@@ -42,9 +42,8 @@
//
// For license information, see the LICENSE file in the current directory.
-#include <sst_config.h>
+#include <core/sst_config.h>
#include <Python.h> // Before serialization to prevent spurious warnings
-#include <sst/core/serialization.h>
#include "gem5.hh"
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/gem5.hh
--- a/ext/sst/gem5.hh Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/gem5.hh Wed Aug 24 14:20:53 2016 +0100
@@ -48,7 +48,6 @@
#include <string>
#include <vector>
-#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/core/output.h>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/libgem5.cc
--- a/ext/sst/libgem5.cc Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/libgem5.cc Wed Aug 24 14:20:53 2016 +0100
@@ -42,9 +42,8 @@
//
// For license information, see the LICENSE file in the current directory.
-#include <sst_config.h>
+#include <core/sst_config.h>
-#include <sst/core/serialization.h>
#include <sst/core/element.h>
#include <sst/core/component.h>
diff -r d726d0cea027 -r a51ae096ca25 ext/sst/tests/test6_arm_4c.py
--- a/ext/sst/tests/test6_arm_4c.py Mon Aug 22 11:43:44 2016 -0400
+++ b/ext/sst/tests/test6_arm_4c.py Wed Aug 24 14:20:53 2016 +0100
@@ -52,18 +52,24 @@
pass
return res
+def debug(d):
+ try:
+ r = int(getenv(d))
+ except ValueError:
+ return 0
+ return r
+
baseCacheParams = ({
- "debug" :getenv("DEBUG"),
+ "debug" :debug("DEBUG"),
"debug_level" : 6,
"coherence_protocol" : "MSI",
"replacement_policy" : "LRU",
"cache_line_size" : 64,
- "cache_frequency" : clockRate,
- "statistics" : 1
+ "cache_frequency" : clockRate
})
l1CacheParams = ({
- "debug" : getenv("DEBUG"),
+ "debug" : debug("DEBUG"),
"debug_level" : 6,
"L1" : 1,
"cache_size" : "64 KB",
@@ -73,7 +79,7 @@
})
l2CacheParams = ({
- "debug" : getenv("DEBUG"),
+ "debug" : debug("DEBUG"),
"debug_level" : 6,
"L1" : 0,
"cache_size" : "256 KB",
@@ -87,8 +93,8 @@
GEM5 = sst.Component("system", "gem5.gem5")
GEM5.addParams({
- "comp_debug" : getenv("GEM5_DEBUG"),
- "gem5DebugFlags" : getenv("M5_DEBUG"),
+ "comp_debug" : debug("GEM5_DEBUG"),
+ "gem5DebugFlags" : debug("M5_DEBUG"),
"frequency" : clockRate,
"cmd" : "configs/example/fs.py --num-cpus 4
--disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img
--root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821
--dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB
--machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst"
})
@@ -96,7 +102,7 @@
bus = sst.Component("membus", "memHierarchy.Bus")
bus.addParams({
"bus_frequency": "2GHz",
- "debug" : getenv("DEBUG"),
+ "debug" : debug("DEBUG"),
"debug_level" : 8
})
@@ -154,8 +160,7 @@
l2cache.addParams(baseCacheParams)
l2cache.addParams(l2CacheParams)
l2cache.addParams({
- "network_address" : "2",
- "directory_at_next_level" : "1"
+ "network_address" : "2"
})
link = sst.Link("l2cache_bus_link")
@@ -168,7 +173,7 @@
"access_time" : "25 ns",
"backend.mem_size" : 256,
"clock" : "2GHz",
- "debug" : getenv("DEBUG"),
+ "debug" : debug("DEBUG"),
"range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
})
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