changeset 2e8d4bd8108d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2e8d4bd8108d
description:
gpu-compute: Wavefront refactoring
Renaming members of the Wavefront class in accordance with the style
guide.
diffstat:
src/arch/hsail/gen.py | 30 +++---
src/arch/hsail/insts/decl.hh | 10 +-
src/arch/hsail/insts/main.cc | 14 +-
src/arch/hsail/insts/mem_impl.hh | 78 +++++++++---------
src/arch/hsail/insts/pseudo_inst.cc | 90 ++++++++++----------
src/gpu-compute/compute_unit.cc | 72 ++++++++--------
src/gpu-compute/dispatcher.cc | 2 +-
src/gpu-compute/fetch_unit.cc | 2 +-
src/gpu-compute/global_memory_pipeline.cc | 6 +-
src/gpu-compute/local_memory_pipeline.cc | 6 +-
src/gpu-compute/wavefront.cc | 130 +++++++++++++++---------------
src/gpu-compute/wavefront.hh | 78 +++++++++---------
12 files changed, 259 insertions(+), 259 deletions(-)
diffs (truncated from 1321 to 300 lines):
diff -r b511733958d0 -r 2e8d4bd8108d src/arch/hsail/gen.py
--- a/src/arch/hsail/gen.py Fri Sep 16 12:26:03 2016 -0400
+++ b/src/arch/hsail/gen.py Fri Sep 16 12:26:52 2016 -0400
@@ -233,7 +233,7 @@
typedef Base::DestCType DestCType;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -254,7 +254,7 @@
typedef Base::DestCType DestCType;
typedef Base::SrcCType SrcCType;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -275,7 +275,7 @@
{
Wavefront *w = gpuDynInst->wavefront();
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -310,7 +310,7 @@
typedef typename Base::Src1CType Src1T;
typedef typename Base::Src2CType Src2T;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -344,7 +344,7 @@
typedef CType Src0T;
typedef typename Base::Src1CType Src1T;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -371,7 +371,7 @@
{
Wavefront *w = gpuDynInst->wavefront();
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
CType dest_val;
@@ -399,7 +399,7 @@
{
Wavefront *w = gpuDynInst->wavefront();
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
@@ -745,17 +745,17 @@
gen(brig_opcode, None, expr, base_class)
-gen_special('WorkItemId', 'w->workitemid[src0][lane]')
+gen_special('WorkItemId', 'w->workItemId[src0][lane]')
gen_special('WorkItemAbsId',
- 'w->workitemid[src0][lane] + (w->workgroupid[src0] *
w->workgroupsz[src0])')
-gen_special('WorkGroupId', 'w->workgroupid[src0]')
-gen_special('WorkGroupSize', 'w->workgroupsz[src0]')
-gen_special('CurrentWorkGroupSize', 'w->workgroupsz[src0]')
-gen_special('GridSize', 'w->gridsz[src0]')
+ 'w->workItemId[src0][lane] + (w->workGroupId[src0] *
w->workGroupSz[src0])')
+gen_special('WorkGroupId', 'w->workGroupId[src0]')
+gen_special('WorkGroupSize', 'w->workGroupSz[src0]')
+gen_special('CurrentWorkGroupSize', 'w->workGroupSz[src0]')
+gen_special('GridSize', 'w->gridSz[src0]')
gen_special('GridGroups',
- 'divCeil(w->gridsz[src0],w->workgroupsz[src0])')
+ 'divCeil(w->gridSz[src0],w->workGroupSz[src0])')
gen_special('LaneId', 'lane')
-gen_special('WaveId', 'w->dynwaveid')
+gen_special('WaveId', 'w->dynWaveId')
gen_special('Clock', 'w->computeUnit->shader->tick_cnt', 'U64')
# gen_special('CU'', ')
diff -r b511733958d0 -r 2e8d4bd8108d src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh Fri Sep 16 12:26:03 2016 -0400
+++ b/src/arch/hsail/insts/decl.hh Fri Sep 16 12:26:52 2016 -0400
@@ -960,7 +960,7 @@
gpuDynInst->simdId = w->simdId;
gpuDynInst->wfSlotId = w->wfSlotId;
gpuDynInst->wfDynId = w->wfDynId;
- gpuDynInst->kern_id = w->kern_id;
+ gpuDynInst->kern_id = w->kernId;
gpuDynInst->cu_id = w->computeUnit->cu_id;
gpuDynInst->memoryOrder =
@@ -971,10 +971,10 @@
GlobalMemPipeline* gmp = &(w->computeUnit->globalMemoryPipe);
gmp->getGMReqFIFO().push(gpuDynInst);
- w->wr_gm_reqs_in_pipe--;
- w->rd_gm_reqs_in_pipe--;
- w->mem_reqs_in_pipe--;
- w->outstanding_reqs++;
+ w->wrGmReqsInPipe--;
+ w->rdGmReqsInPipe--;
+ w->memReqsInPipe--;
+ w->outstandingReqs++;
} else if (o_type == Enums::OT_SHARED_MEMFENCE) {
// no-op
} else {
diff -r b511733958d0 -r 2e8d4bd8108d src/arch/hsail/insts/main.cc
--- a/src/arch/hsail/insts/main.cc Fri Sep 16 12:26:03 2016 -0400
+++ b/src/arch/hsail/insts/main.cc Fri Sep 16 12:26:52 2016 -0400
@@ -131,12 +131,12 @@
{
Wavefront *w = gpuDynInst->wavefront();
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
// mask off completed work-items
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
if (mask[lane]) {
- w->init_mask[lane] = 0;
+ w->initMask[lane] = 0;
}
}
@@ -149,14 +149,14 @@
}
// if all work-items have completed, then wave-front is done
- if (w->init_mask.none()) {
+ if (w->initMask.none()) {
w->status = Wavefront::S_STOPPED;
int32_t refCount = w->computeUnit->getLds().
- decreaseRefCounter(w->dispatchid, w->wg_id);
+ decreaseRefCounter(w->dispatchId, w->wgId);
DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n",
- w->computeUnit->cu_id, w->wg_id, refCount);
+ w->computeUnit->cu_id, w->wgId, refCount);
// free the vector registers of the completed wavefront
w->computeUnit->vectorRegsReserved[w->simdId] -=
@@ -201,8 +201,8 @@
{
Wavefront *w = gpuDynInst->wavefront();
- assert(w->barrier_cnt == w->old_barrier_cnt);
- w->barrier_cnt = w->old_barrier_cnt + 1;
+ assert(w->barrierCnt == w->oldBarrierCnt);
+ w->barrierCnt = w->oldBarrierCnt + 1;
w->stalledAtBarrier = true;
}
} // namespace HsailISA
diff -r b511733958d0 -r 2e8d4bd8108d src/arch/hsail/insts/mem_impl.hh
--- a/src/arch/hsail/insts/mem_impl.hh Fri Sep 16 12:26:03 2016 -0400
+++ b/src/arch/hsail/insts/mem_impl.hh Fri Sep 16 12:26:52 2016 -0400
@@ -59,7 +59,7 @@
Wavefront *w = gpuDynInst->wavefront();
typedef typename DestDataType::CType CType M5_VAR_USED;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
std::vector<Addr> addr_vec;
addr_vec.resize(w->computeUnit->wfSize(), (Addr)0);
this->addr.calcVector(w, addr_vec);
@@ -159,7 +159,7 @@
Wavefront *w = gpuDynInst->wavefront();
typedef typename MemDataType::CType MemCType;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
// Kernarg references are handled uniquely for now (no Memory Request
// is used), so special-case them up front. Someday we should
@@ -230,7 +230,7 @@
m->simdId = w->simdId;
m->wfSlotId = w->wfSlotId;
m->wfDynId = w->wfDynId;
- m->kern_id = w->kern_id;
+ m->kern_id = w->kernId;
m->cu_id = w->computeUnit->cu_id;
m->latency.init(&w->computeUnit->shader->tick_cnt);
@@ -261,8 +261,8 @@
}
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
- w->outstanding_reqs_rd_gm++;
- w->rd_gm_reqs_in_pipe--;
+ w->outstandingReqsRdGm++;
+ w->rdGmReqsInPipe--;
break;
case Brig::BRIG_SEGMENT_SPILL:
@@ -281,14 +281,14 @@
m->addr[lane] = m->addr[lane] * w->spillWidth +
lane * sizeof(MemCType) + w->spillBase;
- w->last_addr[lane] = m->addr[lane];
+ w->lastAddr[lane] = m->addr[lane];
}
}
}
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
- w->outstanding_reqs_rd_gm++;
- w->rd_gm_reqs_in_pipe--;
+ w->outstandingReqsRdGm++;
+ w->rdGmReqsInPipe--;
break;
case Brig::BRIG_SEGMENT_GROUP:
@@ -296,8 +296,8 @@
m->pipeId = LDSMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(24));
w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
- w->outstanding_reqs_rd_lm++;
- w->rd_lm_reqs_in_pipe--;
+ w->outstandingReqsRdLm++;
+ w->rdLmReqsInPipe--;
break;
case Brig::BRIG_SEGMENT_READONLY:
@@ -313,8 +313,8 @@
}
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
- w->outstanding_reqs_rd_gm++;
- w->rd_gm_reqs_in_pipe--;
+ w->outstandingReqsRdGm++;
+ w->rdGmReqsInPipe--;
break;
case Brig::BRIG_SEGMENT_PRIVATE:
@@ -332,8 +332,8 @@
}
}
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
- w->outstanding_reqs_rd_gm++;
- w->rd_gm_reqs_in_pipe--;
+ w->outstandingReqsRdGm++;
+ w->rdGmReqsInPipe--;
break;
default:
@@ -341,8 +341,8 @@
m->addr[0]);
}
- w->outstanding_reqs++;
- w->mem_reqs_in_pipe--;
+ w->outstandingReqs++;
+ w->memReqsInPipe--;
}
template<typename OperationType, typename SrcDataType,
@@ -355,7 +355,7 @@
typedef typename OperationType::CType CType;
- const VectorMask &mask = w->get_pred();
+ const VectorMask &mask = w->getPred();
// arg references are handled uniquely for now (no Memory Request
// is used), so special-case them up front. Someday we should
@@ -419,7 +419,7 @@
m->simdId = w->simdId;
m->wfSlotId = w->wfSlotId;
m->wfDynId = w->wfDynId;
- m->kern_id = w->kern_id;
+ m->kern_id = w->kernId;
m->cu_id = w->computeUnit->cu_id;
m->latency.init(&w->computeUnit->shader->tick_cnt);
@@ -448,8 +448,8 @@
}
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
- w->outstanding_reqs_wr_gm++;
- w->wr_gm_reqs_in_pipe--;
+ w->outstandingReqsWrGm++;
+ w->wrGmReqsInPipe--;
break;
case Brig::BRIG_SEGMENT_SPILL:
@@ -469,8 +469,8 @@
}
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