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Review request for Default. Repository: gem5 Description ------- Changeset 11650:da2261db36a3 --------------------------- riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. Signed-off by: Alec Roelke Diffs ----- src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/formats.isa PRE-CREATION src/arch/riscv/isa/formats/mem.isa PRE-CREATION src/arch/riscv/isa/main.isa PRE-CREATION src/arch/riscv/isa/micro.isa PRE-CREATION src/arch/riscv/isa/operands.isa PRE-CREATION src/arch/riscv/types.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3629/diff/ Testing ------- Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
