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Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights. Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures? ext/libelf/elf_common.h (line 175) <http://reviews.gem5.org/r/3624/#comment7554> Would be good to stick to the same spacing, and not change the AARCH64 line src/arch/riscv/faults.hh (line 139) <http://reviews.gem5.org/r/3624/#comment7555> Could you perhaps elaborate on why this is ok as is? src/arch/riscv/faults.cc (line 62) <http://reviews.gem5.org/r/3624/#comment7556> odd indentation here src/arch/riscv/faults.cc (line 70) <http://reviews.gem5.org/r/3624/#comment7557> odd indentation src/arch/riscv/idle_event.hh (line 47) <http://reviews.gem5.org/r/3624/#comment7558> Not that it matters, but could you update this as well? src/arch/riscv/isa/base.isa (line 3) <http://reviews.gem5.org/r/3624/#comment7566> ? Is that a legal entity? src/arch/riscv/isa/bitfields.isa (line 3) <http://reviews.gem5.org/r/3624/#comment7567> Same as above src/arch/riscv/mmapped_ipr.hh (line 43) <http://reviews.gem5.org/r/3624/#comment7559> RISCV has mmapped IPRs? src/arch/riscv/pagetable.hh (line 81) <http://reviews.gem5.org/r/3624/#comment7560> What are the implications? Also, should this class not inherint from Serializable? src/arch/riscv/process.hh (line 32) <http://reviews.gem5.org/r/3624/#comment7561> ARCH_RISCV_... src/arch/riscv/process.cc (line 116) <http://reviews.gem5.org/r/3624/#comment7562> This block has some formatting issues. Space around operators, and I think it is officially a convention to also keep the operator on the line of the first operand. src/arch/riscv/tlb.cc (line 3) <http://reviews.gem5.org/r/3624/#comment7565> I am really surprise that this and a few other files do not have a Uni Virginia copyright. Is that intentional? src/arch/riscv/tlb.cc (line 58) <http://reviews.gem5.org/r/3624/#comment7563> Not convention src/arch/riscv/tlb.cc (line 89) <http://reviews.gem5.org/r/3624/#comment7564> ? - Andreas Hansson On Sept. 16, 2016, 4:49 p.m., Alec Roelke wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3624/ > ----------------------------------------------------------- > > (Updated Sept. 16, 2016, 4:49 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11620:3da42ffa5b4b > --------------------------- > arch: [Patch 1/5] Added RISC-V base instruction set RV64I > > First of five patches adding RISC-V to GEM5. This patch introduces the > base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. > The multiply, floating point, and atomic memory instructions will be added > in additional patches, as well as support for more detailed CPU models. > The loader is also modified to be able to parse RISC-V ELF files, and a > "Hello world!" example for RISC-V is added to test-progs. > > Patch 2 will implement the multiply extension, RV64M; patch 3 will implement > the floating point (single- and double-precision) extensions, RV64FD; > patch 4 will implement the atomic memory instructions, RV64A, and patch 5 > will add support for timing, minor, and detailed CPU models that is missing > from the first four patches (such as handling locked memory). > > [Removed several unused parameters and imports from RiscvInterrupts.py, > RiscvISA.py, and RiscvSystem.py.] > [Fixed copyright information in RISC-V files copied from elsewhere that had > ARM licenses attached.] > [Reorganized instruction definitions in decoder.isa so that they are sorted > by opcode in preparation for the addition of ISA extensions M, A, F, D.] > Signed-off by: Alec Roelke > > > Diffs > ----- > > src/arch/riscv/stacktrace.hh PRE-CREATION > src/arch/riscv/mmapped_ipr.hh PRE-CREATION > src/arch/riscv/pagetable.hh PRE-CREATION > src/arch/riscv/pagetable.cc PRE-CREATION > build_opts/RISCV PRE-CREATION > ext/libelf/elf_common.h 8bc53d5565ba > src/arch/riscv/RiscvISA.py PRE-CREATION > src/arch/riscv/RiscvInterrupts.py PRE-CREATION > src/arch/riscv/RiscvSystem.py PRE-CREATION > src/arch/riscv/RiscvTLB.py PRE-CREATION > src/arch/riscv/SConscript PRE-CREATION > src/arch/riscv/SConsopts PRE-CREATION > src/arch/riscv/decoder.hh PRE-CREATION > src/arch/riscv/decoder.cc PRE-CREATION > src/arch/riscv/faults.hh PRE-CREATION > src/arch/riscv/faults.cc PRE-CREATION > src/arch/riscv/idle_event.hh PRE-CREATION > src/arch/riscv/idle_event.cc PRE-CREATION > src/arch/riscv/interrupts.hh PRE-CREATION > src/arch/riscv/interrupts.cc PRE-CREATION > src/arch/riscv/isa.hh PRE-CREATION > src/arch/riscv/isa.cc PRE-CREATION > src/arch/riscv/isa/base.isa PRE-CREATION > src/arch/riscv/isa/bitfields.isa PRE-CREATION > src/arch/riscv/isa/decoder.isa PRE-CREATION > src/arch/riscv/isa/formats/basic.isa PRE-CREATION > src/arch/riscv/isa/formats/formats.isa PRE-CREATION > src/arch/riscv/isa/formats/mem.isa PRE-CREATION > src/arch/riscv/isa/formats/type.isa PRE-CREATION > src/arch/riscv/isa/formats/unknown.isa PRE-CREATION > src/arch/riscv/isa/includes.isa PRE-CREATION > src/arch/riscv/isa/main.isa PRE-CREATION > src/arch/riscv/isa/operands.isa PRE-CREATION > src/arch/riscv/isa_traits.hh PRE-CREATION > src/arch/riscv/kernel_stats.hh PRE-CREATION > src/arch/riscv/linux/linux.hh PRE-CREATION > src/arch/riscv/linux/linux.cc PRE-CREATION > src/arch/riscv/linux/process.hh PRE-CREATION > src/arch/riscv/linux/process.cc PRE-CREATION > src/arch/riscv/locked_mem.hh PRE-CREATION > src/arch/riscv/microcode_rom.hh PRE-CREATION > src/arch/riscv/pra_constants.hh PRE-CREATION > src/arch/riscv/process.hh PRE-CREATION > src/arch/riscv/process.cc PRE-CREATION > src/arch/riscv/pseudo_inst.hh PRE-CREATION > src/arch/riscv/registers.hh PRE-CREATION > src/arch/riscv/remote_gdb.hh PRE-CREATION > src/arch/riscv/remote_gdb.cc PRE-CREATION > src/arch/riscv/tlb.hh PRE-CREATION > src/arch/riscv/tlb.cc PRE-CREATION > src/arch/riscv/types.hh PRE-CREATION > src/arch/riscv/utility.hh PRE-CREATION > src/arch/riscv/vtophys.hh PRE-CREATION > src/base/loader/elf_object.cc 8bc53d5565ba > src/base/loader/object_file.hh 8bc53d5565ba > src/cpu/BaseCPU.py 8bc53d5565ba > src/sim/process.cc 8bc53d5565ba > tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba > src/arch/riscv/stacktrace.cc PRE-CREATION > src/arch/riscv/system.hh PRE-CREATION > src/arch/riscv/system.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/3624/diff/ > > > Testing > ------- > > > Thanks, > > Alec Roelke > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
