----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3654/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 11681:ffd318a89635 --------------------------- gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() for HSAIL an operand's indices into the register files may be calculated trivially, because the operands are always read from a register file, or are an immediate. for machine ISA, however, an op selector may specify special registers, or may specify special SGPRs with an alias op selector value. the location of some of the special registers values are dependent on the size of the RF in some cases. here we add a way for the underlying getRegisterIndex() method to know about the size of the RFs, so that it may find the relative positions of the special register values. Diffs ----- src/arch/hsail/insts/decl.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/arch/hsail/insts/mem.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/condition_register_state.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/condition_register_state.cc 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/gpu_dyn_inst.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/gpu_dyn_inst.cc 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/gpu_static_inst.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/gpu-compute/vector_register_file.cc 220fa4099b9a91526b8a1828f27cf1a9f3c15837 src/arch/hsail/insts/branch.hh 220fa4099b9a91526b8a1828f27cf1a9f3c15837 Diff: http://reviews.gem5.org/r/3654/diff/ Testing ------- Thanks, Tony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
