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(Updated Oct. 13, 2016, 4:50 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11659:7209212c989e --------------------------- riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] Signed-off by: Alec Roelke Diffs (updated) ----- build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3630/diff/ Testing ------- Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
