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Ship it!


Looks good to me. It would be good if someone else could review this as well.

- Andreas Hansson


On Oct. 13, 2016, 4:48 p.m., Alec Roelke wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3624/
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> 
> (Updated Oct. 13, 2016, 4:48 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 11655:fce68047f694
> ---------------------------
> arch: [Patch 1/5] Added RISC-V base instruction set RV64I
> 
> First of five patches adding RISC-V to GEM5. This patch introduces the
> base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
> The multiply, floating point, and atomic memory instructions will be added
> in additional patches, as well as support for more detailed CPU models.
> The loader is also modified to be able to parse RISC-V ELF files, and a
> "Hello world!" example for RISC-V is added to test-progs.
> 
> Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
> the floating point (single- and double-precision) extensions, RV64FD;
> patch 4 will implement the atomic memory instructions, RV64A, and patch 5
> will add support for timing, minor, and detailed CPU models that is missing
> from the first four patches (such as handling locked memory).
> 
> [Removed several unused parameters and imports from RiscvInterrupts.py,
> RiscvISA.py, and RiscvSystem.py.]
> [Fixed copyright information in RISC-V files copied from elsewhere that had
> ARM licenses attached.]
> [Reorganized instruction definitions in decoder.isa so that they are sorted
> by opcode in preparation for the addition of ISA extensions M, A, F, D.]
> [Fixed formatting of several files, removed some variables and
> instructions that were missed when moving them to other patches, fixed
> RISC-V Foundation copyright attribution, and fixed history of files
> copied from other architectures using hg copy.]
> [Fixed indentation of switch cases in isa.cc.]
> [Reorganized syscall descriptions in linux/process.cc to remove large
> number of repeated unimplemented system calls and added implmementations
> to functions that have received them since it process.cc was first
> created.]
> [Fixed spacing for some copyright attributions.]
> [Replaced the rest of the file copies using hg copy.]
> Signed-off by: Alec Roelke
> 
> 
> Diffs
> -----
> 
>   build_opts/RISCV PRE-CREATION 
>   ext/libelf/elf_common.h 49cbf4bb0d36 
>   src/arch/riscv/RiscvISA.py PRE-CREATION 
>   src/arch/riscv/RiscvInterrupts.py PRE-CREATION 
>   src/arch/riscv/RiscvSystem.py PRE-CREATION 
>   src/arch/riscv/RiscvTLB.py PRE-CREATION 
>   src/arch/riscv/SConscript PRE-CREATION 
>   src/arch/riscv/SConsopts PRE-CREATION 
>   src/arch/riscv/decoder.hh PRE-CREATION 
>   src/arch/riscv/decoder.cc PRE-CREATION 
>   src/arch/riscv/faults.hh PRE-CREATION 
>   src/arch/riscv/faults.cc PRE-CREATION 
>   src/arch/riscv/idle_event.hh PRE-CREATION 
>   src/arch/riscv/idle_event.cc PRE-CREATION 
>   src/arch/riscv/interrupts.hh PRE-CREATION 
>   src/arch/riscv/interrupts.cc PRE-CREATION 
>   src/arch/riscv/isa.hh PRE-CREATION 
>   src/arch/riscv/isa.cc PRE-CREATION 
>   src/arch/riscv/isa/base.isa PRE-CREATION 
>   src/arch/riscv/isa/bitfields.isa PRE-CREATION 
>   src/arch/riscv/isa/decoder.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/basic.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/formats.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/mem.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/type.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/unknown.isa PRE-CREATION 
>   src/arch/riscv/isa/includes.isa PRE-CREATION 
>   src/arch/riscv/isa/main.isa PRE-CREATION 
>   src/arch/riscv/isa/operands.isa PRE-CREATION 
>   src/arch/riscv/isa_traits.hh PRE-CREATION 
>   src/arch/riscv/kernel_stats.hh PRE-CREATION 
>   src/arch/riscv/linux/linux.hh PRE-CREATION 
>   src/arch/riscv/linux/linux.cc PRE-CREATION 
>   src/arch/riscv/linux/process.hh PRE-CREATION 
>   src/arch/riscv/linux/process.cc PRE-CREATION 
>   src/arch/riscv/locked_mem.hh PRE-CREATION 
>   src/arch/riscv/microcode_rom.hh PRE-CREATION 
>   src/arch/riscv/mmapped_ipr.hh PRE-CREATION 
>   src/arch/riscv/pagetable.hh PRE-CREATION 
>   src/arch/riscv/pagetable.cc PRE-CREATION 
>   src/arch/riscv/pra_constants.hh PRE-CREATION 
>   src/arch/riscv/process.hh PRE-CREATION 
>   src/arch/riscv/process.cc PRE-CREATION 
>   src/arch/riscv/pseudo_inst.hh PRE-CREATION 
>   src/arch/riscv/registers.hh PRE-CREATION 
>   src/arch/riscv/remote_gdb.hh PRE-CREATION 
>   src/arch/riscv/remote_gdb.cc PRE-CREATION 
>   src/arch/riscv/stacktrace.hh PRE-CREATION 
>   src/arch/riscv/stacktrace.cc PRE-CREATION 
>   src/arch/riscv/system.hh PRE-CREATION 
>   src/arch/riscv/system.cc PRE-CREATION 
>   src/arch/riscv/tlb.hh PRE-CREATION 
>   src/arch/riscv/tlb.cc PRE-CREATION 
>   src/arch/riscv/types.hh PRE-CREATION 
>   src/arch/riscv/utility.hh PRE-CREATION 
>   src/arch/riscv/vtophys.hh PRE-CREATION 
>   src/base/loader/elf_object.cc 49cbf4bb0d36 
>   src/base/loader/object_file.hh 49cbf4bb0d36 
>   src/cpu/BaseCPU.py 49cbf4bb0d36 
>   src/sim/process.cc 49cbf4bb0d36 
>   tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36 
> 
> Diff: http://reviews.gem5.org/r/3624/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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