changeset 9f3ccf96bb5a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9f3ccf96bb5a
description:
        mem: add DRAM powerdown timing

diffstat:

 src/mem/DRAMCtrl.py  |  30 ++++++++++++++++++++++++++++++
 src/mem/dram_ctrl.cc |   3 ++-
 src/mem/dram_ctrl.hh |   2 ++
 3 files changed, 34 insertions(+), 1 deletions(-)

diffs (90 lines):

diff -r 55276af429ed -r 9f3ccf96bb5a src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py       Thu Oct 13 19:22:10 2016 +0100
+++ b/src/mem/DRAMCtrl.py       Thu Oct 13 19:22:10 2016 +0100
@@ -370,6 +370,12 @@
     # <=85C, half for >85C
     tREFI = '7.8us'
 
+    # active powerdown and precharge powerdown exit time
+    tXP = '6ns'
+
+    # self refresh exit time
+    tXS = '270ns'
+
     # Current values from datasheet
     IDD0 = '75mA'
     IDD2N = '50mA'
@@ -591,6 +597,12 @@
     # <=85C, half for >85C
     tREFI = '7.8us'
 
+    # active powerdown and precharge powerdown exit time
+    tXP = '6ns'
+
+    # self refresh exit time
+    tXS = '120ns'
+
     # Current values from datasheet
     IDD0 = '70mA'
     IDD02 = '4.6mA'
@@ -659,6 +671,12 @@
     tRFC = '130ns'
     tREFI = '3.9us'
 
+    # active powerdown and precharge powerdown exit time
+    tXP = '7.5ns'
+
+    # self refresh exit time
+    tXS = '140ns'
+
     # Irrespective of speed grade, tWTR is 7.5 ns
     tWTR = '7.5ns'
 
@@ -815,6 +833,12 @@
     tRFC = '130ns'
     tREFI = '3.9us'
 
+    # active powerdown and precharge powerdown exit time
+    tXP = '7.5ns'
+
+    # self refresh exit time
+    tXS = '140ns'
+
     # Irrespective of speed grade, tWTR is 7.5 ns
     tWTR = '7.5ns'
 
@@ -1057,3 +1081,9 @@
     # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
     tCS = '2ns'
     tREFI = '3.9us'
+
+    # active powerdown and precharge powerdown exit time
+    tXP = '10ns'
+
+    # self refresh exit time
+    tXS = '65ns'
diff -r 55276af429ed -r 9f3ccf96bb5a src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc      Thu Oct 13 19:22:10 2016 +0100
+++ b/src/mem/dram_ctrl.cc      Thu Oct 13 19:22:10 2016 +0100
@@ -82,7 +82,8 @@
     tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
     tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
     tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
-    tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit),
+    tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS),
+    activationLimit(p->activation_limit),
     memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
     pageMgmt(p->page_policy),
     maxAccessesPerRow(p->max_accesses_per_row),
diff -r 55276af429ed -r 9f3ccf96bb5a src/mem/dram_ctrl.hh
--- a/src/mem/dram_ctrl.hh      Thu Oct 13 19:22:10 2016 +0100
+++ b/src/mem/dram_ctrl.hh      Thu Oct 13 19:22:10 2016 +0100
@@ -726,6 +726,8 @@
     const Tick tRRD;
     const Tick tRRD_L;
     const Tick tXAW;
+    const Tick tXP;
+    const Tick tXS;
     const uint32_t activationLimit;
 
     /**
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