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Review request for Default. Repository: gem5 Description ------- Changeset 11701:93773f0980da --------------------------- syscall_emul: [patch 13/22] add system call retry capability This changeset adds functionality that allows system calls to retry without affecting system state during on system call returns. We need this functionality to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. For example, consider two processes that are producer/consumer. They can use file descriptors and read/write to pass the information between one another. However if the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue and deadlock the simulation. The trick it to recognize that the system calls will block and then reschedule at some later point when the call would succeed without blocking. In subsequent patches, we recognize that a syscall will' block by calling a non-blocking poll and check for events. This version only supports X86 and will break the other ISAs. I am posting it with the hope that someone can tell me which instructions the other ISAs use to implement their system calls and also to get feedback on the general methodology. Diffs ----- configs/example/se.py 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/arch/x86/isa/decoder/one_byte_opcodes.isa 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/arch/x86/isa/decoder/two_byte_opcodes.isa 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/arch/x86/process.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/arch/x86/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/arch/x86/pseudo_inst.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/BaseCPU.py 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/base.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/base.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/checker/cpu.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/checker/thread_context.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/exec_context.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/commit.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/commit_impl.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/cpu.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/cpu.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/dyn_inst.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/dyn_inst_impl.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/thread_context.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/o3/thread_state.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/simple/atomic.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/simple/exec_context.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/simple/timing.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/simple_thread.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/cpu/thread_context.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/sim/faults.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/sim/faults.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/sim/process.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/sim/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 src/sim/syscall_desc.hh PRE-CREATION src/sim/syscall_desc.cc PRE-CREATION Diff: http://reviews.gem5.org/r/3680/diff/ Testing ------- Thanks, Brandon Potter _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
