changeset e772fdcd3809 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e772fdcd3809
description:
gpu-compute: remove inst enums and use bit flag for attributes
this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple set of attribute flags that can be set in the base
instruction class are used. this will help unify the attributes of HSAIL
and machine ISA instructions within the model itself.
because the static instrution now carries the attributes, a GPUDynInst
must carry a pointer to a valid GPUStaticInst so a new static kernel
launch
instruction is added, which carries the attributes needed to perform a
the kernel launch.
diffstat:
src/arch/hsail/SConscript | 1 -
src/arch/hsail/generic_types.cc | 47 --
src/arch/hsail/generic_types.hh | 16 -
src/arch/hsail/insts/branch.hh | 14 +-
src/arch/hsail/insts/decl.hh | 125 +++++-
src/arch/hsail/insts/main.cc | 5 +-
src/arch/hsail/insts/mem.cc | 63 --
src/arch/hsail/insts/mem.hh | 648 ++++++++++++++---------------
src/arch/hsail/insts/mem_impl.hh | 25 -
src/arch/hsail/insts/pseudo_inst.cc | 31 +-
src/gpu-compute/GPU.py | 108 -----
src/gpu-compute/GPUStaticInstFlags.py | 111 +++++
src/gpu-compute/SConscript | 1 +
src/gpu-compute/code_enums.hh | 116 -----
src/gpu-compute/compute_unit.cc | 26 +-
src/gpu-compute/compute_unit.hh | 1 +
src/gpu-compute/global_memory_pipeline.cc | 23 +-
src/gpu-compute/gpu_dyn_inst.cc | 382 ++++++++++++++++-
src/gpu-compute/gpu_dyn_inst.hh | 215 ++++-----
src/gpu-compute/gpu_static_inst.cc | 6 +-
src/gpu-compute/gpu_static_inst.hh | 169 ++++++-
src/gpu-compute/kernel_cfg.cc | 10 +-
src/gpu-compute/lds_state.cc | 7 +-
src/gpu-compute/lds_state.hh | 1 -
src/gpu-compute/local_memory_pipeline.cc | 9 +-
src/gpu-compute/shader.hh | 1 -
src/gpu-compute/vector_register_file.cc | 5 +-
src/gpu-compute/wavefront.cc | 207 ++------
28 files changed, 1257 insertions(+), 1116 deletions(-)
diffs (truncated from 3777 to 300 lines):
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/SConscript
--- a/src/arch/hsail/SConscript Wed Oct 26 22:47:05 2016 -0400
+++ b/src/arch/hsail/SConscript Wed Oct 26 22:47:11 2016 -0400
@@ -43,7 +43,6 @@
env.Command(['insts/gen_decl.hh', 'gpu_decoder.cc', 'insts/gen_exec.cc'],
'gen.py', '$SOURCE $TARGETS')
- Source('generic_types.cc')
Source('gpu_decoder.cc')
Source('insts/branch.cc')
Source('insts/gen_exec.cc')
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/generic_types.cc
--- a/src/arch/hsail/generic_types.cc Wed Oct 26 22:47:05 2016 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-#include "arch/hsail/generic_types.hh"
-#include "base/misc.hh"
-
-using namespace Brig;
-
-namespace HsailISA
-{
- Enums::GenericMemoryOrder
- getGenericMemoryOrder(BrigMemoryOrder brig_memory_order)
- {
- switch(brig_memory_order) {
- case BRIG_MEMORY_ORDER_NONE:
- return Enums::MEMORY_ORDER_NONE;
- case BRIG_MEMORY_ORDER_RELAXED:
- return Enums::MEMORY_ORDER_RELAXED;
- case BRIG_MEMORY_ORDER_SC_ACQUIRE:
- return Enums::MEMORY_ORDER_SC_ACQUIRE;
- case BRIG_MEMORY_ORDER_SC_RELEASE:
- return Enums::MEMORY_ORDER_SC_RELEASE;
- case BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
- return Enums::MEMORY_ORDER_SC_ACQUIRE_RELEASE;
- default:
- fatal("HsailISA::MemInst::getGenericMemoryOrder -> ",
- "bad BrigMemoryOrder\n");
- }
- }
-
- Enums::GenericMemoryScope
- getGenericMemoryScope(BrigMemoryScope brig_memory_scope)
- {
- switch(brig_memory_scope) {
- case BRIG_MEMORY_SCOPE_NONE:
- return Enums::MEMORY_SCOPE_NONE;
- case BRIG_MEMORY_SCOPE_WORKITEM:
- return Enums::MEMORY_SCOPE_WORKITEM;
- case BRIG_MEMORY_SCOPE_WORKGROUP:
- return Enums::MEMORY_SCOPE_WORKGROUP;
- case BRIG_MEMORY_SCOPE_AGENT:
- return Enums::MEMORY_SCOPE_DEVICE;
- case BRIG_MEMORY_SCOPE_SYSTEM:
- return Enums::MEMORY_SCOPE_SYSTEM;
- default:
- fatal("HsailISA::MemInst::getGenericMemoryScope -> ",
- "bad BrigMemoryScope\n");
- }
- }
-} // namespace HsailISA
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/generic_types.hh
--- a/src/arch/hsail/generic_types.hh Wed Oct 26 22:47:05 2016 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,16 +0,0 @@
-#ifndef __ARCH_HSAIL_GENERIC_TYPES_HH__
-#define __ARCH_HSAIL_GENERIC_TYPES_HH__
-
-#include "arch/hsail/Brig.h"
-#include "enums/GenericMemoryOrder.hh"
-#include "enums/GenericMemoryScope.hh"
-
-namespace HsailISA
-{
- Enums::GenericMemoryOrder
- getGenericMemoryOrder(Brig::BrigMemoryOrder brig_memory_order);
- Enums::GenericMemoryScope
- getGenericMemoryScope(Brig::BrigMemoryScope brig_memory_scope);
-} // namespace HsailISA
-
-#endif // __ARCH_HSAIL_GENERIC_TYPES_HH__
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hh Wed Oct 26 22:47:05 2016 -0400
+++ b/src/arch/hsail/insts/branch.hh Wed Oct 26 22:47:11 2016 -0400
@@ -59,16 +59,15 @@
BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "brn")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
+ setFlag(UnconditionalJump);
width = ((Brig::BrigInstBr*)ib)->width;
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
- bool unconditionalJumpInstruction() override { return true; }
bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister();
@@ -175,13 +174,12 @@
CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "cbr")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
width = ((Brig::BrigInstBr *)ib)->width;
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
cond.init(op_offs, obj);
op_offs = obj->getOperandPtr(ib->operands, 1);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
@@ -343,17 +341,15 @@
BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "br")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
+ setFlag(UnconditionalJump);
width.init(((Brig::BrigInstBr *)ib)->width, obj);
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
- bool unconditionalJumpInstruction() override { return true; }
-
void execute(GPUDynInstPtr gpuDynInst) override;
bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh Wed Oct 26 22:47:05 2016 -0400
+++ b/src/arch/hsail/insts/decl.hh Wed Oct 26 22:47:11 2016 -0400
@@ -38,11 +38,9 @@
#include <cmath>
-#include "arch/hsail/generic_types.hh"
#include "arch/hsail/insts/gpu_static_inst.hh"
#include "arch/hsail/operand.hh"
#include "debug/HSAIL.hh"
-#include "enums/OpType.hh"
#include "gpu-compute/gpu_dyn_inst.hh"
#include "gpu-compute/shader.hh"
@@ -127,6 +125,8 @@
const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -240,6 +240,8 @@
const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -414,6 +416,8 @@
const BrigObject *obj, const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -818,6 +822,8 @@
const BrigObject *obj, const char *_opcode)
: HsailGPUStaticInst(obj, _opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -874,7 +880,7 @@
Ret(const Brig::BrigInstBase *ib, const BrigObject *obj)
: Base(ib, obj, "ret")
{
- o_type = Enums::OT_RET;
+ setFlag(GPUStaticInst::Return);
}
void execute(GPUDynInstPtr gpuDynInst);
@@ -889,7 +895,7 @@
Barrier(const Brig::BrigInstBase *ib, const BrigObject *obj)
: Base(ib, obj, "barrier")
{
- o_type = Enums::OT_BARRIER;
+ setFlag(GPUStaticInst::MemBarrier);
assert(ib->base.kind == Brig::BRIG_KIND_INST_BR);
width = (uint8_t)((Brig::BrigInstBr*)ib)->width;
}
@@ -924,14 +930,105 @@
memFenceMemOrder = (Brig::BrigMemoryOrder)
((Brig::BrigInstMemFence*)ib)->memoryOrder;
- // set o_type based on scopes
+ setFlag(MemoryRef);
+ setFlag(GPUStaticInst::MemFence);
+
+ switch (memFenceMemOrder) {
+ case Brig::BRIG_MEMORY_ORDER_NONE:
+ setFlag(NoOrder);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_RELAXED:
+ setFlag(RelaxedOrder);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_ACQUIRE:
+ setFlag(Acquire);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_RELEASE:
+ setFlag(Release);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
+ setFlag(AcquireRelease);
+ break;
+ default:
+ fatal("MemInst has bad BrigMemoryOrder\n");
+ }
+
+ // set inst flags based on scopes
if (memFenceScopeSegGlobal != Brig::BRIG_MEMORY_SCOPE_NONE &&
memFenceScopeSegGroup != Brig::BRIG_MEMORY_SCOPE_NONE) {
- o_type = Enums::OT_BOTH_MEMFENCE;
+ setFlag(GPUStaticInst::GlobalSegment);
+
+ /**
+ * A memory fence that has scope for
+ * both segments will use the global
+ * segment, and be executed in the
+ * global memory pipeline, therefore,
+ * we set the segment to match the
+ * global scope only
+ */
+ switch (memFenceScopeSegGlobal) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("MemFence has bad global scope type\n");
+ }
} else if (memFenceScopeSegGlobal != Brig::BRIG_MEMORY_SCOPE_NONE)
{
- o_type = Enums::OT_GLOBAL_MEMFENCE;
+ setFlag(GPUStaticInst::GlobalSegment);
+
+ switch (memFenceScopeSegGlobal) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("MemFence has bad global scope type\n");
+ }
} else if (memFenceScopeSegGroup != Brig::BRIG_MEMORY_SCOPE_NONE) {
- o_type = Enums::OT_SHARED_MEMFENCE;
+ setFlag(GPUStaticInst::GroupSegment);
+
+ switch (memFenceScopeSegGroup) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
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