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util/tlm/README (line 4) <http://reviews.gem5.org/r/3527/#comment7758> Both directions are implemented, Initiator (Master) and Target (Slave) util/tlm/examples/slave_port/sc_target.cc (line 61) <http://reviews.gem5.org/r/3527/#comment7759> once the patch is accepted i will change this to something like this: ```c++ unsigned int size = 1024 * 1024 * 1024; memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); ``` - Matthias Jung On Okt. 28, 2016, 12:27 nachm., Christian Menard wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3527/ > ----------------------------------------------------------- > > (Updated Okt. 28, 2016, 12:27 nachm.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > The current TLM code only provides a Slave Port that allows the gem5 world to > send requests to the the TLM world. This patch restructures the existing > source code in util/tlm in order to allow for code reuse and a clear file > structure whenn adding a master port implementation. It also replaces the > Makefile by a SConstruct. > > > Diffs > ----- > > util/tlm/tlm.py b3d5f0e9e258 > util/tlm/tlm_elastic.py b3d5f0e9e258 > util/tlm/sim_control.cc PRE-CREATION > util/tlm/tgen.cfg b3d5f0e9e258 > util/tlm/sc_target.hh b3d5f0e9e258 > util/tlm/sc_target.cc b3d5f0e9e258 > util/tlm/sim_control.hh PRE-CREATION > util/tlm/sc_mm.cc b3d5f0e9e258 > util/tlm/sc_port.hh b3d5f0e9e258 > util/tlm/sc_port.cc b3d5f0e9e258 > util/tlm/sc_slave_port.hh PRE-CREATION > util/tlm/sc_slave_port.cc PRE-CREATION > util/tlm/sc_ext.hh b3d5f0e9e258 > util/tlm/sc_ext.cc b3d5f0e9e258 > util/tlm/sc_mm.hh b3d5f0e9e258 > util/tlm/examples/slave_port/tlm_elastic.py PRE-CREATION > util/tlm/main.cc b3d5f0e9e258 > util/tlm/run_gem5.sh b3d5f0e9e258 > util/tlm/examples/slave_port/run_gem5.sh PRE-CREATION > util/tlm/examples/slave_port/sc_target.hh PRE-CREATION > util/tlm/examples/slave_port/sc_target.cc PRE-CREATION > util/tlm/examples/slave_port/tgen.cfg PRE-CREATION > util/tlm/examples/slave_port/tlm.py PRE-CREATION > configs/common/MemConfig.py b3d5f0e9e258 > util/tlm/Makefile b3d5f0e9e258 > util/tlm/README b3d5f0e9e258 > util/tlm/examples/slave_port/SConstruct PRE-CREATION > util/tlm/examples/slave_port/main.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/3527/diff/ > > > Testing > ------- > > The examples provided in util/tlm (now util/tlm/examples/slave_port) still > compile and run error free. > > > Thanks, > > Christian Menard > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
