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Review request for Default. Repository: gem5 Description ------- Changeset 11719:a12bce848e83 --------------------------- mem: Respond to InvalidateReq when the block is (pending) dirty Previously when an InvalidateReq snooped a cache with a dirty block or a pending modified MSHR, it would invalidate the block or set the postInv flag. The cache would not send an InvalidateResp. though, causing memory order violations. This patches changes this behavior, making the cache with the dirty block or pending modified MSHR the ordering point. Change-Id: Ib4c31012f4f6693ffb137cd77258b160fbc239ca Reviewed-by: Andreas Hansson <[email protected]> Diffs ----- src/mem/cache/cache.cc 1d085f66c4ca src/mem/cache/mshr.cc 1d085f66c4ca Diff: http://reviews.gem5.org/r/3735/diff/ Testing ------- Thanks, Nikos Nikoleris _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
