Hi Alec, These are ready according to me. Unless someone has an objection, I'll push them on Friday (assuming I can get up after all the food on Thursday).
Note: All of the tests are passing for me with minor changes in the instruction rates, etc. Thanks again for these patches. I think that this is one of the most important additions to gem5 in a while :). Cheers, Jason On Sun, Nov 20, 2016 at 2:20 PM Alec Roelke <[email protected]> wrote: > Hello Everyone, > > It has been about two weeks since the last review for my 8 RISC-V patches > except the 7th patch, so it seems to me like most of them can be > committed? The patches are: > - 3624 (arch: [Patch 1/5] Added RISC-V base instruction set RV64I) > - 3627 (riscv: [Patch 2/5] Added RISC-V multiply extension RV64M) > - 3628 (riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD) > - 3629 (riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A) > - 3630 (riscv: [Patch 5/5] Added missing support for timing CPU models) > - 3668 (riscv: [Patch 6/5] Improve Linux emulation for RISC-V) > - 3693 (riscv: [Patch 7/5] Corrected LRSC semantics) > - 3694 (riscv: [Patch 8/5] Added some regression tests to RISC-V) > > There is a bug that sometimes occurs with the O3 CPU model where a memory > access may cross a cache line boundary (see the first comment chain of > patch 3693) and cause a panic. I have not encountered this except when > trying to run some of the regression tests I made for patch 3694 on O3. It > would make the most sense to change patch 3624 to fix it, but since that > would delay shipping it, I think it would be better to make a new patch. > > Thanks, > Alec Roelke > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
