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Ship it! Ship It! - Jason Lowe-Power On April 26, 2016, 12:42 p.m., Arthur Perais wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3453/ > ----------------------------------------------------------- > > (Updated April 26, 2016, 12:42 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11459:faf70a6f13ed > ---------------------------- > > o3: Clarify meaning of cachePorts variable in lsq_unit.hh > > cachePorts currently constrains the number of store packets written to the > D-Cache each cycle), but loads currently affect this variable. This leads > to unexpected congestion (e.g., setting cachePorts to a realistic 1 will > in fact allow a store to WB only if no loads have accessed the D-Cache > this cycle). In the absence of arbitration, this patch decouples how many > loads can be done per cycle from how many stores can be done per cycle. > > > Diffs > ----- > > src/cpu/o3/O3CPU.py 91834ba4b16d > src/cpu/o3/lsq_unit.hh 91834ba4b16d > src/cpu/o3/lsq_unit_impl.hh 91834ba4b16d > > Diff: http://reviews.gem5.org/r/3453/diff/ > > > Testing > ------- > > util/regress -v --builds=ARM passes with 0% differences (expected: cachePorts > defaults to 200, so functionally, the patch changes nothing for the default > parameters). > > > Thanks, > > Arthur Perais > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
