changeset 0d7119bed18e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0d7119bed18e
description:
arm: audit SCTLR
Change-Id: I814f1431a5f754f75721c9ac51171f860a714d24
Reviewed-by: Andreas Sandberg <[email protected]>
diffstat:
src/arch/arm/isa.cc | 25 ++++++++++---------------
1 files changed, 10 insertions(+), 15 deletions(-)
diffs (70 lines):
diff -r ec57caae355e -r 0d7119bed18e src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Dec 19 11:03:27 2016 -0600
+++ b/src/arch/arm/isa.cc Mon Dec 19 11:03:27 2016 -0600
@@ -211,9 +211,7 @@
pmu(p->pmu),
lookUpMiscReg(NUM_MISCREGS, {0,0})
{
- SCTLR sctlr;
- sctlr = 0;
- miscRegs[MISCREG_SCTLR_RST] = sctlr;
+ miscRegs[MISCREG_SCTLR_RST] = 0;
// Hook up a dummy device if we haven't been configured with a
// real PMU. By using a dummy device, we don't need to check that
@@ -432,12 +430,14 @@
// Initialize other control registers
miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
if (haveSecurity) {
- miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
+ miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
} else if (haveVirtualization) {
- miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
+ // also MISCREG_SCTLR_EL2 (by mapping)
+ miscRegs[MISCREG_HSCTLR] = 0x30c50830;
} else {
- miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
+ // also MISCREG_SCTLR_EL1 (by mapping)
+ miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
// Always non-secure
miscRegs[MISCREG_SCR_EL3] = 1;
}
@@ -491,12 +491,9 @@
// registers are left unchanged
MiscReg val;
- if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR
- || flat_idx == MISCREG_SCTLR_EL1) {
+ if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR) {
if (flat_idx == MISCREG_SPSR)
flat_idx = flattenMiscIndex(MISCREG_SPSR);
- if (flat_idx == MISCREG_SCTLR_EL1)
- flat_idx = flattenMiscIndex(MISCREG_SCTLR);
val = miscRegs[flat_idx];
} else
if (lookUpMiscReg[flat_idx].upper > 0)
@@ -779,11 +776,11 @@
case MISCREG_SCTLR:
return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
case MISCREG_SCTLR_EL1:
- return (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800;
+ return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
+ case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
+ case MISCREG_HSCTLR:
return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
- case MISCREG_HSCTLR:
- return readMiscRegNoEffect(MISCREG_HSCTLR);
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
@@ -817,8 +814,6 @@
} else {
if (flat_idx == MISCREG_SPSR)
flat_idx = flattenMiscIndex(MISCREG_SPSR);
- else if (flat_idx == MISCREG_SCTLR_EL1)
- flat_idx = flattenMiscIndex(MISCREG_SCTLR);
else
flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
lookUpMiscReg[flat_idx].lower : flat_idx;
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