changeset 4b62a0bf0168 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4b62a0bf0168
description:
arm: provide correct timer availability in ID_PFR1 register
Change-Id: Id4cd839c12b70616017a5830e3f9bbb59b0f97ba
Reviewed-by: Andreas Sandberg <[email protected]>
diffstat:
src/arch/arm/isa.cc | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diffs (21 lines):
diff -r 9db50b9eacf5 -r 4b62a0bf0168 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Dec 19 11:03:28 2016 -0600
+++ b/src/arch/arm/isa.cc Mon Dec 19 11:03:28 2016 -0600
@@ -770,10 +770,13 @@
// !ThumbEE | !Jazelle | Thumb | ARM
return 0x00000031;
case MISCREG_ID_PFR1:
- // !Timer | Virti | !M Profile | TrustZone | ARMv4
- return 0x00000001
- | (haveSecurity ? 0x00000010 : 0x0)
- | (haveVirtualization ? 0x00001000 : 0x0);
+ { // Timer | Virti | !M Profile | TrustZone | ARMv4
+ bool haveTimer = (system->getGenericTimer() != NULL);
+ return 0x00000001
+ | (haveSecurity ? 0x00000010 : 0x0)
+ | (haveVirtualization ? 0x00001000 : 0x0)
+ | (haveTimer ? 0x00010000 : 0x0);
+ }
case MISCREG_ID_AA64PFR0_EL1:
return 0x0000000000000002 // AArch{64,32} supported at EL0
| 0x0000000000000020 // EL1
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
