> On Jan. 18, 2017, 3:21 p.m., Jason Lowe-Power wrote: > > While you're on this code, I have a question. Maybe Andreas H. can answer > > too. Why are all of the configurations for the memory controllers in > > src/mem/DRAMCtrl.py? They could all be in configs/dram_ctrls/*.py, right? > > > > It seems to me that the DRAMCtrl.py file is getting a little out of hand. > > Is there any reason not to move all of the specific DRAM controller timing > > definitions to new files in the config/ directory? > > Matthew Poremba wrote: > Correct me if I'm wrong, but DRAMCtrl.py is currently built as a > SimObject, so shouldn't any splits of this file be under src/? I believe > right now the config scripts may require this to do automatic discovery for > --mem-type.
My point was that "DDR4_2400_16x4" is not a SimObject declaration (whereas DRAMCtrl is). There is almost certainly no technical reason not to have DDR4_2400_16x4 in configs/. For the --mem-type, this could be implemented by adding a map in some config file with each of the controller types, though I'm sure we could be more clever about it if we wanted to. Currently DRAMCtrl.py is almost 1200 lines, and only about 300 of those lines are the SimObject declaration. I was recently doing some work with the DRAMCtrl and trying to update or add new memory types was a pain. Spliting this out into multiple files and putting these files in configs/ would have made it simpler. - Jason ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3783/#review9254 ----------------------------------------------------------- On Jan. 17, 2017, 10:04 p.m., Curtis Dunham wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3783/ > ----------------------------------------------------------- > > (Updated Jan. 17, 2017, 10:04 p.m.) > > > Review request for Default and Matthias Jung. > > > Repository: gem5 > > > Description > ------- > > mem: Update DRAM configuration names > > Names of DRAM configurations were updated to reflect both > the channel and device data width. > > Previous naming format was: > <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> > > The following nomenclature is now used: > <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> > where n = The number of devices per rank on the channel > x = Device width > > Total channel width can be calculated by n*w > > Example: > A 64-bit DDR4, 2400 channel consisting of 4-bit devices: > n = 16 > w = 4 > The resulting configuration name is: > DDR4_2400_16x4 > > Updated scripts to match new naming convention. > > Added unique configurations for DDR4 for: > 1) 16x4 > 2) 8x8 > 3) 4x16 > > Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 > Reviewed-by: Radhika Jagtap <[email protected]> > Reviewed-by: Curtis Dunham <[email protected]> > > > Diffs > ----- > > tests/configs/realview-simple-timing-dual.py 97eebddaae84 > tests/configs/realview-simple-timing.py 97eebddaae84 > tests/configs/realview-switcheroo-full.py 97eebddaae84 > tests/configs/realview-switcheroo-o3.py 97eebddaae84 > tests/configs/realview-switcheroo-timing.py 97eebddaae84 > tests/configs/realview64-minor-dual.py 97eebddaae84 > tests/configs/realview64-minor.py 97eebddaae84 > tests/configs/realview64-o3-checker.py 97eebddaae84 > tests/configs/o3-timing-checker.py 97eebddaae84 > tests/configs/o3-timing-mp.py 97eebddaae84 > tests/configs/o3-timing-mt.py 97eebddaae84 > tests/configs/o3-timing.py 97eebddaae84 > tests/configs/pc-o3-timing.py 97eebddaae84 > tests/configs/pc-simple-timing.py 97eebddaae84 > tests/configs/pc-switcheroo-full.py 97eebddaae84 > tests/configs/realview-minor-dual.py 97eebddaae84 > tests/configs/realview-minor.py 97eebddaae84 > tests/configs/realview-o3-checker.py 97eebddaae84 > tests/configs/realview-o3-dual.py 97eebddaae84 > tests/configs/realview-o3.py 97eebddaae84 > src/mem/DRAMCtrl.py 97eebddaae84 > tests/configs/minor-timing-mp.py 97eebddaae84 > tests/configs/minor-timing.py 97eebddaae84 > configs/example/memcheck.py 97eebddaae84 > configs/learning_gem5/part1/simple.py 97eebddaae84 > configs/learning_gem5/part1/two_level.py 97eebddaae84 > configs/common/HMC.py 97eebddaae84 > configs/common/MemConfig.py 97eebddaae84 > configs/common/Options.py 97eebddaae84 > configs/dram/lat_mem_rd.py 97eebddaae84 > configs/dram/sweep.py 97eebddaae84 > configs/example/hmctest.py 97eebddaae84 > tests/configs/realview64-o3-dual.py 97eebddaae84 > tests/configs/realview64-o3.py 97eebddaae84 > tests/configs/realview64-simple-timing-dual.py 97eebddaae84 > tests/configs/realview64-simple-timing.py 97eebddaae84 > tests/configs/realview64-switcheroo-full.py 97eebddaae84 > tests/configs/realview64-switcheroo-o3.py 97eebddaae84 > tests/configs/realview64-switcheroo-timing.py 97eebddaae84 > tests/configs/tgen-dram-ctrl.py 97eebddaae84 > tests/configs/tsunami-minor-dual.py 97eebddaae84 > tests/configs/tsunami-minor.py 97eebddaae84 > tests/configs/tsunami-o3-dual.py 97eebddaae84 > tests/configs/tsunami-o3.py 97eebddaae84 > tests/configs/tsunami-simple-timing-dual.py 97eebddaae84 > tests/configs/tsunami-simple-timing.py 97eebddaae84 > tests/configs/tsunami-switcheroo-full.py 97eebddaae84 > > Diff: http://reviews.gem5.org/r/3783/diff/ > > > Testing > ------- > > > Thanks, > > Curtis Dunham > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
