> On Jan. 19, 2017, 10:13 p.m., Jason Lowe-Power wrote: > > src/cpu/reg_class_impl.hh, line 1 > > <http://reviews.gem5.org/r/3754/diff/1/?file=64440#file64440line1> > > > > Why is this an implemenation header file?
Because it is something that can/should be inlined, as the control has dependence on things that can be optimized at compile-time. On the other hand, as it depends on 'TheISA', having the implementation in the header file would make the reg_class.hh depend on the ISA, and that leads to some compile time issues due to cyclic dependencies. Having as separate implementation file is a compromise solution that keeps the dependencies to the minimum required, while still providing the code for inlining to have the minimum impact on performance. - Rekai ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3754/#review9284 ----------------------------------------------------------- On Jan. 16, 2017, 11:46 a.m., Rekai Gonzalez Alberquilla wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3754/ > ----------------------------------------------------------- > > (Updated Jan. 16, 2017, 11:46 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11760:686a5d1464b6 > --------------------------- > cpu: Simplify the rename interface and use RegId > > With the hierarchical RegId there are a lot of functions that are > redundant now. > > The idea behind the simplification is that instead of having the regId, > telling which kind of register read/write/rename/lookup/etc. and then > the function panic_if'ing if the regId is not of the appropriate type, > what we ahve is an interface that you give it the regId, and depending > on the type of register, it decides which kind of register to read... > > Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 > Reviewed-by: Andreas Sandberg <[email protected]> > > > Diffs > ----- > > src/arch/x86/insts/microregop.hh 78ef8daecd81 > src/arch/x86/insts/static_inst.hh 78ef8daecd81 > src/arch/x86/insts/static_inst.cc 78ef8daecd81 > src/arch/x86/isa.hh 78ef8daecd81 > src/arch/x86/isa/microops/limmop.isa 78ef8daecd81 > src/cpu/base_dyn_inst.hh 78ef8daecd81 > src/cpu/checker/cpu.hh 78ef8daecd81 > src/cpu/checker/cpu_impl.hh 78ef8daecd81 > src/cpu/checker/thread_context.hh 78ef8daecd81 > src/cpu/exec_context.hh 78ef8daecd81 > src/cpu/minor/dyn_inst.cc 78ef8daecd81 > src/cpu/minor/exec_context.hh 78ef8daecd81 > src/cpu/minor/scoreboard.hh 78ef8daecd81 > src/cpu/minor/scoreboard.cc 78ef8daecd81 > src/cpu/o3/comm.hh 78ef8daecd81 > src/cpu/o3/cpu.cc 78ef8daecd81 > src/cpu/o3/dyn_inst.hh 78ef8daecd81 > src/cpu/o3/free_list.hh 78ef8daecd81 > src/cpu/o3/iew_impl.hh 78ef8daecd81 > src/cpu/o3/inst_queue_impl.hh 78ef8daecd81 > src/cpu/o3/probe/elastic_trace.cc 78ef8daecd81 > src/cpu/o3/regfile.hh 78ef8daecd81 > src/cpu/o3/regfile.cc 78ef8daecd81 > src/cpu/o3/rename.hh 78ef8daecd81 > src/cpu/o3/rename_impl.hh 78ef8daecd81 > src/cpu/o3/rename_map.hh 78ef8daecd81 > src/cpu/o3/rename_map.cc 78ef8daecd81 > src/cpu/o3/scoreboard.hh 78ef8daecd81 > src/cpu/o3/thread_context.hh 78ef8daecd81 > src/cpu/o3/thread_context_impl.hh 78ef8daecd81 > src/cpu/reg_class.hh 78ef8daecd81 > src/cpu/reg_class.cc 78ef8daecd81 > src/cpu/reg_class_impl.hh PRE-CREATION > src/cpu/simple/exec_context.hh 78ef8daecd81 > src/cpu/simple_thread.hh 78ef8daecd81 > src/cpu/static_inst.hh 78ef8daecd81 > src/cpu/thread_context.hh 78ef8daecd81 > src/cpu/timing_expr.cc 78ef8daecd81 > src/arch/alpha/isa.hh 78ef8daecd81 > src/arch/alpha/isa/branch.isa 78ef8daecd81 > src/arch/alpha/isa/fp.isa 78ef8daecd81 > src/arch/alpha/isa/main.isa 78ef8daecd81 > src/arch/arm/insts/misc.cc 78ef8daecd81 > src/arch/arm/isa.hh 78ef8daecd81 > src/arch/arm/isa.cc 78ef8daecd81 > src/arch/arm/isa/insts/data64.isa 78ef8daecd81 > src/arch/arm/isa/insts/fp.isa 78ef8daecd81 > src/arch/arm/isa/insts/misc.isa 78ef8daecd81 > src/arch/mips/isa.hh 78ef8daecd81 > src/arch/mips/isa/base.isa 78ef8daecd81 > src/arch/mips/isa/formats/int.isa 78ef8daecd81 > src/arch/power/insts/branch.cc 78ef8daecd81 > src/arch/power/insts/static_inst.cc 78ef8daecd81 > src/arch/power/isa.hh 78ef8daecd81 > src/arch/sparc/isa.hh 78ef8daecd81 > src/arch/sparc/isa/base.isa 78ef8daecd81 > src/arch/sparc/isa/formats/integerop.isa 78ef8daecd81 > src/arch/sparc/isa/formats/mem/util.isa 78ef8daecd81 > src/arch/sparc/isa/formats/priv.isa 78ef8daecd81 > src/arch/x86/insts/microfpop.hh 78ef8daecd81 > src/arch/x86/insts/microldstop.hh 78ef8daecd81 > src/arch/x86/insts/micromediaop.hh 78ef8daecd81 > > Diff: http://reviews.gem5.org/r/3754/diff/ > > > Testing > ------- > > Built in regressions passing > > > Thanks, > > Rekai Gonzalez Alberquilla > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
