changeset 17b37f38944a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=17b37f38944a
description:
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both
the channel and device data width.
Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width
Total channel width can be calculated by n*w
Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <[email protected]>
Reviewed-by: Curtis Dunham <[email protected]>
diffstat:
configs/common/HMC.py | 2 +-
configs/common/MemConfig.py | 4 +-
configs/common/Options.py | 2 +-
configs/dram/lat_mem_rd.py | 2 +-
configs/dram/sweep.py | 4 +-
configs/example/hmctest.py | 4 +-
configs/example/memcheck.py | 2 +-
configs/learning_gem5/part1/simple.py | 2 +-
configs/learning_gem5/part1/two_level.py | 2 +-
src/mem/DRAMCtrl.py | 165 ++++++++++++++++++------
tests/configs/minor-timing-mp.py | 2 +-
tests/configs/minor-timing.py | 2 +-
tests/configs/o3-timing-checker.py | 2 +-
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing-mt.py | 4 +-
tests/configs/o3-timing.py | 4 +-
tests/configs/pc-o3-timing.py | 2 +-
tests/configs/pc-simple-timing.py | 2 +-
tests/configs/pc-switcheroo-full.py | 2 +-
tests/configs/realview-minor-dual.py | 2 +-
tests/configs/realview-minor.py | 2 +-
tests/configs/realview-o3-checker.py | 2 +-
tests/configs/realview-o3-dual.py | 2 +-
tests/configs/realview-o3.py | 2 +-
tests/configs/realview-simple-timing-dual.py | 2 +-
tests/configs/realview-simple-timing.py | 2 +-
tests/configs/realview-switcheroo-full.py | 2 +-
tests/configs/realview-switcheroo-o3.py | 2 +-
tests/configs/realview-switcheroo-timing.py | 2 +-
tests/configs/realview64-minor-dual.py | 2 +-
tests/configs/realview64-minor.py | 2 +-
tests/configs/realview64-o3-checker.py | 2 +-
tests/configs/realview64-o3-dual.py | 2 +-
tests/configs/realview64-o3.py | 2 +-
tests/configs/realview64-simple-timing-dual.py | 2 +-
tests/configs/realview64-simple-timing.py | 2 +-
tests/configs/realview64-switcheroo-full.py | 2 +-
tests/configs/realview64-switcheroo-o3.py | 2 +-
tests/configs/realview64-switcheroo-timing.py | 2 +-
tests/configs/tgen-dram-ctrl.py | 2 +-
tests/configs/tsunami-minor-dual.py | 2 +-
tests/configs/tsunami-minor.py | 2 +-
tests/configs/tsunami-o3-dual.py | 2 +-
tests/configs/tsunami-o3.py | 2 +-
tests/configs/tsunami-simple-timing-dual.py | 2 +-
tests/configs/tsunami-simple-timing.py | 2 +-
tests/configs/tsunami-switcheroo-full.py | 2 +-
47 files changed, 171 insertions(+), 96 deletions(-)
diffs (truncated from 813 to 300 lines):
diff -r 3195e72010da -r 17b37f38944a configs/common/HMC.py
--- a/configs/common/HMC.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/common/HMC.py Tue Feb 14 15:09:18 2017 -0600
@@ -58,7 +58,7 @@
# serial links, the main internal crossbar, and an external hmc controller.
#
# - VAULT CONTROLLERS:
-# Instances of the HMC_2500_x32 class with their functionality specified in
+# Instances of the HMC_2500_1x32 class with their functionality specified in
# dram_ctrl.cc
#
# - THE MAIN XBAR:
diff -r 3195e72010da -r 17b37f38944a configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/common/MemConfig.py Tue Feb 14 15:09:18 2017 -0600
@@ -152,7 +152,7 @@
them.
"""
- if ( options.mem_type == "HMC_2500_x32"):
+ if ( options.mem_type == "HMC_2500_1x32"):
HMChost = HMC.config_host_hmc(options, system)
HMC.config_hmc(options, system, HMChost.hmc_host)
subsystem = system.hmc_dev
@@ -223,7 +223,7 @@
# Connect the controllers to the membus
for i in xrange(len(subsystem.mem_ctrls)):
- if (options.mem_type == "HMC_2500_x32"):
+ if (options.mem_type == "HMC_2500_1x32"):
subsystem.mem_ctrls[i].port = xbar[i/4].master
else:
subsystem.mem_ctrls[i].port = xbar.master
diff -r 3195e72010da -r 17b37f38944a configs/common/Options.py
--- a/configs/common/Options.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/common/Options.py Tue Feb 14 15:09:18 2017 -0600
@@ -77,7 +77,7 @@
parser.add_option("--list-mem-types",
action="callback", callback=_listMemTypes,
help="List available memory types")
- parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+ parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")
parser.add_option("--mem-channels", type="int", default=1,
diff -r 3195e72010da -r 17b37f38944a configs/dram/lat_mem_rd.py
--- a/configs/dram/lat_mem_rd.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/dram/lat_mem_rd.py Tue Feb 14 15:09:18 2017 -0600
@@ -80,7 +80,7 @@
parser = optparse.OptionParser()
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")
parser.add_option("--mem-size", action="store", type="string",
diff -r 3195e72010da -r 17b37f38944a configs/dram/sweep.py
--- a/configs/dram/sweep.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/dram/sweep.py Tue Feb 14 15:09:18 2017 -0600
@@ -53,8 +53,8 @@
parser = optparse.OptionParser()
-# Use a single-channel DDR3-1600 x64 by default
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
help = "type of memory to use")
diff -r 3195e72010da -r 17b37f38944a configs/example/hmctest.py
--- a/configs/example/hmctest.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/example/hmctest.py Tue Feb 14 15:09:18 2017 -0600
@@ -13,8 +13,8 @@
parser = optparse.OptionParser()
-# Use a HMC_2500_x32 by default
-parser.add_option("--mem-type", type = "choice", default = "HMC_2500_x32",
+# Use a HMC_2500_1x32 (1 channel, 32-bits wide) by default
+parser.add_option("--mem-type", type = "choice", default = "HMC_2500_1x32",
choices = MemConfig.mem_names(),
help = "type of memory to use")
diff -r 3195e72010da -r 17b37f38944a configs/example/memcheck.py
--- a/configs/example/memcheck.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/example/memcheck.py Tue Feb 14 15:09:18 2017 -0600
@@ -216,7 +216,7 @@
proto_tester = TrafficGen(config_file = cfg_file_name)
# Set up the system along with a DRAM controller
-system = System(physmem = DDR3_1600_x64())
+system = System(physmem = DDR3_1600_8x8())
system.voltage_domain = VoltageDomain(voltage = '1V')
diff -r 3195e72010da -r 17b37f38944a configs/learning_gem5/part1/simple.py
--- a/configs/learning_gem5/part1/simple.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/learning_gem5/part1/simple.py Tue Feb 14 15:09:18 2017 -0600
@@ -75,7 +75,7 @@
system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus
-system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
diff -r 3195e72010da -r 17b37f38944a configs/learning_gem5/part1/two_level.py
--- a/configs/learning_gem5/part1/two_level.py Tue Feb 14 15:09:18 2017 -0600
+++ b/configs/learning_gem5/part1/two_level.py Tue Feb 14 15:09:18 2017 -0600
@@ -128,7 +128,7 @@
system.system_port = system.membus.slave
# Create a DDR3 memory controller
-system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
diff -r 3195e72010da -r 17b37f38944a src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py Tue Feb 14 15:09:18 2017 -0600
+++ b/src/mem/DRAMCtrl.py Tue Feb 14 15:09:18 2017 -0600
@@ -315,7 +315,7 @@
# A single DDR3-1600 x64 channel (one command and address bus), with
# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
# an 8x8 configuration.
-class DDR3_1600_x64(DRAMCtrl):
+class DDR3_1600_8x8(DRAMCtrl):
# size of device in bytes
device_size = '512MB'
@@ -410,7 +410,7 @@
# configuration.
# This configuration includes the latencies from the DRAM to the logic layer
# of the HMC
-class HMC_2500_x32(DDR3_1600_x64):
+class HMC_2500_1x32(DDR3_1600_8x8):
# size of device
# two banks per device with each bank 4MB [2]
device_size = '8MB'
@@ -492,7 +492,7 @@
# options for the DDR-1600 configuration, based on the same DDR3-1600
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
# consistent across the two configurations.
-class DDR3_2133_x64(DDR3_1600_x64):
+class DDR3_2133_8x8(DDR3_1600_8x8):
# 1066 MHz
tCK = '0.938ns'
@@ -520,35 +520,37 @@
VDD = '1.5V'
# A single DDR4-2400 x64 channel (one command and address bus), with
-# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
-# in an 4x16 configuration.
-class DDR4_2400_x64(DRAMCtrl):
+# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
+# in an 16x4 configuration.
+# Total channel capacity is 32GB
+# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
+class DDR4_2400_16x4(DRAMCtrl):
# size of device
- device_size = '512MB'
+ device_size = '1GB'
- # 4x16 configuration, 4 devices each with an 16-bit interface
- device_bus_width = 16
+ # 16x4 configuration, 16 devices each with a 4-bit interface
+ device_bus_width = 4
# DDR4 is a BL8 device
burst_length = 8
- # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
- device_rowbuffer_size = '2kB'
+ # Each device has a page (row buffer) size of 512 byte (1K columns x4)
+ device_rowbuffer_size = '512B'
- # 4x16 configuration, so 4 devices
- devices_per_rank = 4
+ # 16x4 configuration, so 16 devices
+ devices_per_rank = 16
# Match our DDR3 configurations which is dual rank
ranks_per_channel = 2
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
- # Set to 2 for x16 case
- bank_groups_per_rank = 2
+ # Set to 4 for x4 case
+ bank_groups_per_rank = 4
# DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
# configurations). Currently we do not capture the additional
# constraints incurred by the bank groups
- banks_per_rank = 8
+ banks_per_rank = 16
# override the default buffer sizes and go for something larger to
# accommodate the larger bank count
@@ -562,7 +564,7 @@
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
# With bank group architectures, tBURST represents the CAS-to-CAS
# delay for bursts to different bank groups (tCCD_S)
- tBURST = '3.333ns'
+ tBURST = '3.332ns'
# @2400 data rate, tCCD_L is 6 CK
# CAS-to-CAS delay for bursts to the same bank group
@@ -570,21 +572,23 @@
# for CAS-to-CAS delay for bursts to different bank groups
tCCD_L = '5ns';
- # DDR4-2400 16-16-16
- tRCD = '13.32ns'
- tCL = '13.32ns'
- tRP = '13.32ns'
- tRAS = '35ns'
+ # DDR4-2400 17-17-17
+ tRCD = '14.16ns'
+ tCL = '14.16ns'
+ tRP = '14.16ns'
+ tRAS = '32ns'
- # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
- tRRD = '5.3ns'
+ # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
+ tRRD = '3.332ns'
- # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
- tRRD_L = '6.4ns';
+ # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
+ tRRD_L = '4.9ns';
- tXAW = '30ns'
+ # tFAW for 512B page is MAX(16 CK, 13ns)
+ tXAW = '13.328ns'
activation_limit = 4
- tRFC = '260ns'
+ # tRFC is 350ns
+ tRFC = '350ns'
tWR = '15ns'
@@ -607,27 +611,98 @@
tXP = '6ns'
# self refresh exit time
- tXS = '120ns'
+ # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
+ # tRFC + 10ns = 340ns
+ tXS = '340ns'
# Current values from datasheet
- IDD0 = '70mA'
- IDD02 = '4.6mA'
- IDD2N = '50mA'
- IDD3N = '67mA'
+ IDD0 = '43mA'
+ IDD02 = '3mA'
+ IDD2N = '34mA'
+ IDD3N = '38mA'
IDD3N2 = '3mA'
- IDD4W = '302mA'
- IDD4R = '230mA'
- IDD5 = '192mA'
- IDD3P1 = '44mA'
- IDD2P1 = '32mA'
- IDD6 = '20mA'
+ IDD4W = '103mA'
+ IDD4R = '110mA'
+ IDD5 = '250mA'
+ IDD3P1 = '32mA'
+ IDD2P1 = '25mA'
+ IDD6 = '30mA'
VDD = '1.2V'
VDD2 = '2.5V'
+# A single DDR4-2400 x64 channel (one command and address bus), with
+# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
+# in an 8x8 configuration.
+# Total channel capacity is 16GB
+# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
+class DDR4_2400_8x8(DDR4_2400_16x4):
+ # 8x8 configuration, 8 devices each with an 8-bit interface
+ device_bus_width = 8
+
+ # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
+ device_rowbuffer_size = '1kB'
+
+ # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
+ tRRD_L = '4.9ns';
+
+ tXAW = '21ns'
+
+ # Current values from datasheet
+ IDD0 = '48mA'
+ IDD3N = '43mA'
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