changeset 0e94e16e26ea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0e94e16e26ea
description:
syscall_emul: [patch 8/22] refactor process class
Moves aux_vector into its own .hh and .cc files just to get it out of
the
already crowded Process files. Arguably, it could stay there, but it's
probably better just to move it and give it files.
The changeset looks ugly around the Process header file, but the goal
here is
to move methods and members around so that they're not defined randomly
throughout the entire header file. I expect this is likely one of the
reasons
why I several unused variables related to this class. So, the methods
are
declared first followed by members. I've tried to aggregate them
together
so that similar entries reside near one another.
There are other changes coming to this code so this is by no means the
final product.
diffstat:
src/arch/alpha/process.cc | 1 +
src/arch/arm/process.cc | 1 +
src/arch/mips/process.cc | 1 +
src/arch/power/process.cc | 1 +
src/arch/riscv/process.cc | 1 +
src/arch/sparc/process.cc | 1 +
src/arch/x86/process.cc | 4 +
src/arch/x86/process.hh | 1 +
src/sim/SConscript | 1 +
src/sim/aux_vector.cc | 77 +++++++++++++
src/sim/aux_vector.hh | 77 +++++++++++++
src/sim/process.cc | 34 ++---
src/sim/process.hh | 259 +++++++++++++++------------------------------
13 files changed, 269 insertions(+), 190 deletions(-)
diffs (truncated from 713 to 300 lines):
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/alpha/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -38,6 +38,7 @@
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/arm/process.cc
--- a/src/arch/arm/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/arm/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -51,6 +51,7 @@
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/mips/process.cc
--- a/src/arch/mips/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/mips/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -39,6 +39,7 @@
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/power/process.cc
--- a/src/arch/power/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/power/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -40,6 +40,7 @@
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/riscv/process.cc
--- a/src/arch/riscv/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/riscv/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -42,6 +42,7 @@
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/sparc/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -42,6 +42,7 @@
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/x86/process.cc
--- a/src/arch/x86/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/x86/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -44,6 +44,9 @@
#include "arch/x86/process.hh"
+#include <string>
+#include <vector>
+
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/segment.hh"
@@ -57,6 +60,7 @@
#include "debug/Stack.hh"
#include "mem/multi_level_page_table.hh"
#include "mem/page_table.hh"
+#include "sim/aux_vector.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/arch/x86/process.hh
--- a/src/arch/x86/process.hh Wed Nov 09 14:27:41 2016 -0600
+++ b/src/arch/x86/process.hh Wed Nov 09 14:27:41 2016 -0600
@@ -43,6 +43,7 @@
#include <string>
#include <vector>
+#include "sim/aux_vector.hh"
#include "sim/process.hh"
#include "mem/multi_level_page_table.hh"
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/sim/SConscript
--- a/src/sim/SConscript Wed Nov 09 14:27:41 2016 -0600
+++ b/src/sim/SConscript Wed Nov 09 14:27:41 2016 -0600
@@ -75,6 +75,7 @@
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
SimObject('Process.py')
+ Source('aux_vector.cc')
Source('faults.cc')
Source('process.cc')
Source('fd_entry.cc')
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/sim/aux_vector.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/sim/aux_vector.cc Wed Nov 09 14:27:41 2016 -0600
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Brandon Potter
+ */
+
+#include "sim/aux_vector.hh"
+
+#include <inttypes.h>
+
+#include "config/the_isa.hh"
+
+#if THE_ISA == ALPHA_ISA
+#include "arch/alpha/linux/process.hh"
+
+#elif THE_ISA == SPARC_ISA
+#include "arch/sparc/linux/process.hh"
+#include "arch/sparc/solaris/process.hh"
+
+#elif THE_ISA == MIPS_ISA
+#include "arch/mips/linux/process.hh"
+
+#elif THE_ISA == ARM_ISA
+#include "arch/arm/freebsd/process.hh"
+#include "arch/arm/linux/process.hh"
+
+#elif THE_ISA == X86_ISA
+#include "arch/x86/linux/process.hh"
+
+#elif THE_ISA == RISCV_ISA
+#include "arch/riscv/linux/process.hh"
+
+#elif THE_ISA == POWER_ISA
+#include "arch/power/linux/process.hh"
+
+#else
+#error "THE_ISA not set"
+#endif
+
+template<class IntType>
+AuxVector<IntType>::AuxVector(IntType type, IntType val)
+{
+ a_type = TheISA::htog(type);
+ a_val = TheISA::htog(val);
+}
+
+template struct AuxVector<uint32_t>;
+template struct AuxVector<uint64_t>;
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/sim/aux_vector.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/sim/aux_vector.hh Wed Nov 09 14:27:41 2016 -0600
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Brandon Potter
+ */
+
+#ifndef __AUX_VECTOR_HH__
+#define __AUX_VECTOR_HH__
+
+template<class IntType>
+struct AuxVector
+{
+ IntType a_type;
+ IntType a_val;
+
+ AuxVector()
+ {}
+
+ AuxVector(IntType type, IntType val);
+};
+
+enum AuxiliaryVectorType {
+ M5_AT_NULL = 0,
+ M5_AT_IGNORE = 1,
+ M5_AT_EXECFD = 2,
+ M5_AT_PHDR = 3,
+ M5_AT_PHENT = 4,
+ M5_AT_PHNUM = 5,
+ M5_AT_PAGESZ = 6,
+ M5_AT_BASE = 7,
+ M5_AT_FLAGS = 8,
+ M5_AT_ENTRY = 9,
+ M5_AT_NOTELF = 10,
+ M5_AT_UID = 11,
+ M5_AT_EUID = 12,
+ M5_AT_GID = 13,
+ M5_AT_EGID = 14,
+ M5_AT_PLATFORM = 15,
+ M5_AT_HWCAP = 16,
+ M5_AT_CLKTCK = 17,
+ M5_AT_SECURE = 23,
+ M5_BASE_PLATFORM = 24,
+ M5_AT_RANDOM = 25,
+ M5_AT_EXECFN = 31,
+ M5_AT_VECTOR_SIZE = 44
+};
+
+#endif // __AUX_VECTOR_HH__
diff -r 4fb5223f1e0c -r 0e94e16e26ea src/sim/process.cc
--- a/src/sim/process.cc Wed Nov 09 14:27:41 2016 -0600
+++ b/src/sim/process.cc Wed Nov 09 14:27:41 2016 -0600
@@ -93,17 +93,6 @@
// current number of allocated processes
int num_processes = 0;
-template<class IntType>
-
-AuxVector<IntType>::AuxVector(IntType type, IntType val)
-{
- a_type = TheISA::htog(type);
- a_val = TheISA::htog(val);
-}
-
-template struct AuxVector<uint32_t>;
-template struct AuxVector<uint64_t>;
-
static int
openFile(const string& filename, int flags, mode_t mode)
{
@@ -205,7 +194,6 @@
}
}
-
void
Process::regStats()
{
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
