changeset 8732d8d0a9e5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8732d8d0a9e5
description:
mem: Fix MSHR assert triggering for invalidated prefetches
This changeset updates an assert in src/mem/cache/mshr.cc which was
erroneously catching invalidated prefetch requests. These requests can
become invalidated if another component writes (an exclusive access)
to this location during the time that the read request is in
flight. The original assert made the assumption that these cases can
only occur for reads generated by the CPU, and hence
prefetcher-generated requests would sometimes trip the assert.
Change-Id: If4f043273a688c2bab8f7a641192a2b583e7b20e
Reviewed-by: Nikos Nikoleris <[email protected]>
Signed-off-by: Andreas Sandberg <[email protected]>
diffstat:
src/mem/cache/mshr.cc | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diffs (20 lines):
diff -r 608f8c34f549 -r 8732d8d0a9e5 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Tue Feb 21 14:14:44 2017 +0000
+++ b/src/mem/cache/mshr.cc Tue Feb 21 14:14:44 2017 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2017 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -465,7 +465,8 @@
// avoid memory consistency violations.
if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
auto it = targets.begin();
- assert(it->source == Target::FromCPU);
+ assert((it->source == Target::FromCPU) ||
+ (it->source == Target::FromPrefetcher));
ready_targets.push_back(*it);
it = targets.erase(it);
while (it != targets.end()) {
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