----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3817/#review9453 -----------------------------------------------------------
Thanks for fixing this! I think we may have independently fixed the SPSR mapping issue by adding mapping in the ISA code. Other than that, there are some minor structural things below. src/arch/arm/kvm/armv8_cpu.cc (line 193) <http://reviews.gem5.org/r/3817/#comment7973> This change shouldn't be needed anymore. The ISA code automatically maps SPSR_EL1 to the same physical register as SPSR_SVC. (See the MiscRegSwitch table in arch/arm/isa.cc) src/arch/arm/kvm/armv8_cpu.cc (line 255) <http://reviews.gem5.org/r/3817/#comment7974> Shouldn't be needed anymore. See comment above. src/arch/arm/kvm/armv8_cpu.cc (line 268) <http://reviews.gem5.org/r/3817/#comment7977> I'd suggest adding something like this instead: const bool in_a64 = inAArch64(tc); That'd remove the need to read out cpsr before the loop above and the special case for CPSR. src/arch/arm/kvm/armv8_cpu.cc (line 308) <http://reviews.gem5.org/r/3817/#comment7976> I don't think this is actually needed. gem5 typically intercepts accesses to INTREG_PC and redirects them to the pcState using a readPC() helper method on the exec context. src/arch/arm/kvm/base_cpu.cc (line 82) <http://reviews.gem5.org/r/3817/#comment7975> What's the reason for setting the PSCI flag? - Andreas Sandberg On Feb. 21, 2017, 5:46 p.m., Rahul Thakur wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3817/ > ----------------------------------------------------------- > > (Updated Feb. 21, 2017, 5:46 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11874:ceed3b2698f6 > --------------------------- > commit 2873a1ea3720e638ba1bb4f7c69b43b98bc4d72a > Author: Slava Malyugin <[email protected]> > Date: Wed Dec 2 19:41:24 2015 -0800 > > arm, kvm: enable running 32-bit Guest under ARM KVM64 > > 1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit > when running 32-bit OS > > 2) Correctly map 64-bit registers to banked 32-bit ones > > 3) Set R15 when PC is changed > > 4) Map MISCREG_SPSR_EL1 to MISCREG_SPSR_SVC in 32-bit mode. > > TEST: built build/ARM/gem5.opt on ARM and x86 > tested with KVM64 on Cortex-A57, restored KVM checkpoint in atomic > mode > BUG: none > > Change-Id: I20d138276f6cc5aff7a855988c2e30dccef5affc > > > Diffs > ----- > > src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 > src/arch/arm/kvm/base_cpu.cc ba90ffa751b6 > > Diff: http://reviews.gem5.org/r/3817/diff/ > > > Testing > ------- > > > Thanks, > > Rahul Thakur > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
