[gem5-dev] Change in public/gem5[master]: riscv: enable unaligned memory accesses

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2341

Change subject: riscv: enable unaligned memory accesses
......................................................................

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
---
M src/arch/riscv/isa_traits.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c87..327d644 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@

 const ExtMachInst NoopMachInst = 0x00000013;

-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory  
accesses)
+const bool HasUnalignedMemAcc = true;

 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;

--
To view, visit https://gem5-review.googlesource.com/2341
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Gerrit-Change-Number: 2341
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev