Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/2620
to review the following change.
Change subject: arm, dev: stub out GIC distributor interrupt groups
......................................................................
arm, dev: stub out GIC distributor interrupt groups
We don't implement the GICD_IGROUPRn registers, which is allowed, but
to be correct, they should be RAZ/WI (read as zero, writes ignored).
Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index c114604..ce27e94 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -52,6 +52,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+const AddrRange Pl390::GICD_IGROUPR (0x080, 0x0ff);
const AddrRange Pl390::GICD_ISENABLER (0x100, 0x17f);
const AddrRange Pl390::GICD_ICENABLER (0x180, 0x1ff);
const AddrRange Pl390::GICD_ISPENDR (0x200, 0x27f);
@@ -153,6 +154,10 @@
uint32_t
Pl390::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
{
+ if (GICD_IGROUPR.contains(daddr)) {
+ return 0; // unimplemented; RAZ (read as zero)
+ }
+
if (GICD_ISENABLER.contains(daddr)) {
uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
assert(ix < 32);
@@ -387,6 +392,10 @@
Pl390::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
size_t data_sz)
{
+ if (GICD_IGROUPR.contains(daddr)) {
+ return; // unimplemented; WI (writes ignored)
+ }
+
if (GICD_ISENABLER.contains(daddr)) {
uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
assert(ix < 32);
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 6f819bf..05c9b5f 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -71,6 +71,7 @@
DIST_SIZE = 0xfff
};
+ static const AddrRange GICD_IGROUPR; // interrupt group
(unimplemented)
static const AddrRange GICD_ISENABLER; // interrupt set enable
static const AddrRange GICD_ICENABLER; // interrupt clear enable
static const AddrRange GICD_ISPENDR; // set pending interrupt
--
To view, visit https://gem5-review.googlesource.com/2620
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Gerrit-Change-Number: 2620
Gerrit-PatchSet: 1
Gerrit-Owner: Curtis Dunham <curtis.dun...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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