Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/2860
Change subject: config: cpu: arm: Process the O3 ARM models as SimObject
source.
......................................................................
config: cpu: arm: Process the O3 ARM models as SimObject source.
There isn't really any reason to set them up at runtime instead of at build
time, and this way they don't have to have special handling in CpuConfig.py.
Change-Id: I943c7f09b07e4d7c11d7f18dbcdbf205a3cf8865
---
R src/arch/arm/cpu/O3CpuModels.py
A src/arch/arm/cpu/SConscript
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/configs/common/O3_ARM_v7a.py b/src/arch/arm/cpu/O3CpuModels.py
similarity index 97%
rename from configs/common/O3_ARM_v7a.py
rename to src/arch/arm/cpu/O3CpuModels.py
index f5c2c71..8a13e6a 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/src/arch/arm/cpu/O3CpuModels.py
@@ -27,7 +27,11 @@
# Authors: Ron Dreslinski
-from m5.objects import *
+from BranchPredictor import *
+from Cache import *
+from FuncUnit import *
+from O3CPU import *
+from Prefetcher import *
# Simple ALU Instructions have a latency of 1
class O3_ARM_v7a_Simple_Int(FUDesc):
diff --git a/src/arch/arm/cpu/SConscript b/src/arch/arm/cpu/SConscript
new file mode 100644
index 0000000..24738b1
--- /dev/null
+++ b/src/arch/arm/cpu/SConscript
@@ -0,0 +1,32 @@
+# Copyright (c) 2017 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+if env['TARGET_ISA'] == 'arm' and 'O3CPU' in env['CPU_MODELS']:
+ SimObject('O3CpuModels.py')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I943c7f09b07e4d7c11d7f18dbcdbf205a3cf8865
Gerrit-Change-Number: 2860
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
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