[gem5-dev] Change in public/gem5[master]: syscall_emul, riscv: add override keyword to RISCV Process c...

[Brandon Potter (Gerrit)]

Brandon Potter has uploaded this change for review. (  
https://gem5-review.googlesource.com/3360

Change subject: syscall_emul, riscv: add override keyword to RISCV Process  
class
......................................................................

syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
---
M src/arch/riscv/process.hh
1 file changed, 6 insertions(+), 4 deletions(-)



diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index f732a44..2a27f35 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -48,17 +48,19 @@
   protected:
     RiscvProcess(ProcessParams * params, ObjectFile *objFile);

-    void initState();
+    void initState() override;

     template<class IntType>
     void argsInit(int pageSize);

   public:
-    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
-    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+    void setSyscallArg(ThreadContext *tc, int i,
+                       RiscvISA::IntReg val) override;
+    void setSyscallReturn(ThreadContext *tc,
+                          SyscallReturn return_value) override;

     virtual bool mmapGrowsDown() const override { return false; }
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Gerrit-Change-Number: 3360
Gerrit-PatchSet: 1
Gerrit-Owner: Brandon Potter <brandon.pot...@amd.com>
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