Gedare Bloom has uploaded this change for review. (
https://gem5-review.googlesource.com/3520
Change subject: arch-arm: fix ldm of pc interswitching branch
......................................................................
arch-arm: fix ldm of pc interswitching branch
The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
---
M src/arch/arm/isa/insts/macromem.isa
M src/arch/arm/isa/operands.isa
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/insts/macromem.isa
b/src/arch/arm/isa/insts/macromem.isa
index cc7366e..6a33d1b 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -58,7 +58,8 @@
microLdr2UopCode = '''
uint64_t data = Mem_ud;
Dest = cSwap((uint32_t) data, ((CPSR)Cpsr).e);
- Dest2 = cSwap((uint32_t) (data >> 32),
((CPSR)Cpsr).e);
+ IWDest2 = cSwap((uint32_t) (data >> 32),
+ ((CPSR)Cpsr).e);
'''
microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop',
'MicroMemPairOp',
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e48c154..b80f3d1 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -181,6 +181,7 @@
'Dest2': intReg('dest2'),
'XDest2': intRegX64('dest2'),
'FDest2': floatReg('dest2'),
+ 'IWDest2': intRegIWPC('dest2'),
'Result': intReg('result'),
'XResult': intRegX64('result'),
'XBase': intRegX64('base', id = srtBase),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Gerrit-Change-Number: 3520
Gerrit-PatchSet: 1
Gerrit-Owner: Gedare Bloom <ged...@rtems.org>
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