Change subject: mips, x86: Refactor some Event subclasses into lambdas ...................................................................... mips, x86: Refactor some Event subclasses into lambdas Change-Id: I09570e569efe55f5502bc201e03456738999e714 Signed-off-by: Sean Wilson <spwils...@wisc.edu> --- M src/arch/mips/isa.cc M src/arch/mips/isa.hh M src/arch/x86/interrupts.cc M src/arch/x86/interrupts.hh 4 files changed, 16 insertions(+), 75 deletions(-) diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 6310f67..df70bac 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -523,7 +523,9 @@ cp0Updated = true; //schedule UPDATE - CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); + auto cp0_event = new EventFunctionWrapper( + [this, cpu]{ processCP0Event(cpu, UpdateCP0); }, + "Coprocessor-0 event", true, Event::CPU_Tick_Pri); cpu->schedule(cp0_event, cpu->clockEdge(delay)); } } @@ -557,40 +559,17 @@ cp0Updated = false; } -ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) - : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) -{ } - void -ISA::CP0Event::process() +ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType) { switch (cp0EventType) { case UpdateCP0: - cp0->updateCPU(cpu); + updateCPU(cpu); break; } } -const char * -ISA::CP0Event::description() const -{ - return "Coprocessor-0 event"; -} - -void -ISA::CP0Event::scheduleEvent(Cycles delay) -{ - cpu->reschedule(this, cpu->clockEdge(delay), true); -} - -void -ISA::CP0Event::unscheduleEvent() -{ - if (scheduled()) - squash(); -} - } MipsISA::ISA * diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index feb55e4..6f5beba 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -117,31 +117,8 @@ UpdateCP0 }; - // Declare A CP0Event Class for scheduling - class CP0Event : public Event - { - protected: - ISA::CP0 *cp0; - BaseCPU *cpu; - CP0EventType cp0EventType; - Fault fault; - - public: - /** Constructs a CP0 event. */ - CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type); - - /** Process this event. */ - virtual void process(); - - /** Returns the description of this event. */ - const char *description() const; - - /** Schedule This Event */ - void scheduleEvent(Cycles delay); - - /** Unschedule This Event */ - void unscheduleEvent(); - }; + /** Process a CP0 event */ + void processCP0Event(BaseCPU *cpu, CP0EventType); // Schedule a CP0 Update Event void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); @@ -150,9 +127,6 @@ // and if necessary alert the CPU void updateCPU(BaseCPU *cpu); - // Keep a List of CPU Events that need to be deallocated - std::queue<CP0Event*> cp0EventRemoveList; - static std::string miscRegNames[NumMiscRegs]; public: diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index b869a92..0ef79a4 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -588,7 +588,7 @@ X86ISA::Interrupts::Interrupts(Params * p) : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency), - apicTimerEvent(this), + apicTimerEvent([this]{ processApicTimerEvent(); }, name()), pendingSmi(false), smiVector(0), pendingNmi(false), nmiVector(0), pendingExtInt(false), extIntVector(0), @@ -767,3 +767,9 @@ { return new X86ISA::Interrupts(this); } + +void +X86ISA::Interrupts::processApicTimerEvent() { + if (triggerTimerInterrupt()) + setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT)); +} diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 26699b0..bfd1889 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -92,26 +92,8 @@ /* * Timing related stuff. */ - class ApicTimerEvent : public Event - { - private: - Interrupts *localApic; - public: - ApicTimerEvent(Interrupts *_localApic) : - Event(), localApic(_localApic) - {} - - void process() - { - assert(localApic); - if (localApic->triggerTimerInterrupt()) { - localApic->setReg(APIC_INITIAL_COUNT, - localApic->readReg(APIC_INITIAL_COUNT)); - } - } - }; - - ApicTimerEvent apicTimerEvent; + EventFunctionWrapper apicTimerEvent; + void processApicTimerEvent(); /* * A set of variables to keep track of interrupts that don't go through -- To view, visit https://gem5-review.googlesource.com/3920 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I09570e569efe55f5502bc201e03456738999e714 Gerrit-Change-Number: 3920 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Wilson <spwils...@wisc.edu> _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Sean Wilson has uploaded this change for review. (
https://gem5-review.googlesource.com/3920
- [gem5-dev] Change in public/gem5[master]: mips, x86: ... Sean Wilson (Gerrit)
- [gem5-dev] Change in public/gem5[master]: mips, ... Sean Wilson (Gerrit)