Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/3943
to review the following change.
Change subject: config: Move core timing models to config/common/cores
......................................................................
config: Move core timing models to config/common/cores
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Gabor Dozsa <[email protected]>
---
M configs/common/CacheConfig.py
M configs/common/CpuConfig.py
A configs/common/cores/__init__.py
R configs/common/cores/arm/O3_ARM_v7a.py
A configs/common/cores/arm/__init__.py
R configs/common/cores/arm/ex5_LITTLE.py
R configs/common/cores/arm/ex5_big.py
M configs/example/arm/fs_bigLITTLE.py
M tests/configs/arm_generic.py
M tests/configs/o3-timing-mt.py
M tests/configs/o3-timing.py
11 files changed, 83 insertions(+), 12 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index d9d0ae7..a0a18a3 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -55,9 +55,9 @@
if options.cpu_type == "O3_ARM_v7a_3":
try:
- from O3_ARM_v7a import *
+ from cores.arm.O3_ARM_v7a import *
except:
- print "arm_detailed is unavailable. Did you compile the O3
model?"
+ print "O3_ARM_v7a_3 is unavailable. Did you compile the O3
model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index eee6a77..4def9fd 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -113,23 +113,23 @@
# The ARM detailed CPU is special in the sense that it doesn't exist
# in the normal object hierarchy, so we have to add it manually.
try:
- from O3_ARM_v7a import O3_ARM_v7a_3
+ from cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
_cpu_classes["O3_ARM_v7a_3"] = O3_ARM_v7a_3
except:
pass
# The calibrated ex5-model cores
try:
- from ex5_LITTLE import ex5_LITTLE
+ from cores.arm.ex5_LITTLE import ex5_LITTLE
_cpu_classes["ex5_LITTLE"] = ex5_LITTLE
except:
- pass
+ pass
try:
- from ex5_big import ex5_big
+ from cores.arm.ex5_big import ex5_big
_cpu_classes["ex5_big"] = ex5_big
except:
- pass
+ pass
# Add all CPUs in the object hierarchy.
diff --git a/configs/common/cores/__init__.py
b/configs/common/cores/__init__.py
new file mode 100644
index 0000000..7a2173e
--- /dev/null
+++ b/configs/common/cores/__init__.py
@@ -0,0 +1,36 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
diff --git a/configs/common/O3_ARM_v7a.py
b/configs/common/cores/arm/O3_ARM_v7a.py
similarity index 100%
rename from configs/common/O3_ARM_v7a.py
rename to configs/common/cores/arm/O3_ARM_v7a.py
diff --git a/configs/common/cores/arm/__init__.py
b/configs/common/cores/arm/__init__.py
new file mode 100644
index 0000000..7a2173e
--- /dev/null
+++ b/configs/common/cores/arm/__init__.py
@@ -0,0 +1,36 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
diff --git a/configs/common/ex5_LITTLE.py
b/configs/common/cores/arm/ex5_LITTLE.py
similarity index 100%
rename from configs/common/ex5_LITTLE.py
rename to configs/common/cores/arm/ex5_LITTLE.py
diff --git a/configs/common/ex5_big.py b/configs/common/cores/arm/ex5_big.py
similarity index 100%
rename from configs/common/ex5_big.py
rename to configs/common/cores/arm/ex5_big.py
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 4f548b1..2965f47 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -51,8 +51,7 @@
from common import SysPaths
from common import CpuConfig
-from common import ex5_big
-from common import ex5_LITTLE
+from common.cores.arm import ex5_big, ex5_LITTLE
import devices
from devices import AtomicCluster, KvmCluster
diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py
index 86ad5d7..722749c 100644
--- a/tests/configs/arm_generic.py
+++ b/tests/configs/arm_generic.py
@@ -43,7 +43,7 @@
from common import FSConfig
from common.Caches import *
from base_config import *
-from common.O3_ARM_v7a import *
+from common.cores.arm.O3_ARM_v7a import *
from common.Benchmarks import SysConfig
class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
diff --git a/tests/configs/o3-timing-mt.py b/tests/configs/o3-timing-mt.py
index 7a829bb..c45510b 100644
--- a/tests/configs/o3-timing-mt.py
+++ b/tests/configs/o3-timing-mt.py
@@ -42,7 +42,7 @@
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 050e405..b9a5181 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -42,7 +42,7 @@
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Gerrit-Change-Number: 3943
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
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