Sean Wilson has uploaded this change for review. ( https://gem5-review.googlesource.com/4000

Change subject: sim, x86: Move tlb flush from copyRegs to clone emulation.
......................................................................

sim, x86: Move tlb flush from copyRegs to clone emulation.

copyRegs should be idempotent so it can be used for swapping CPUs.
However, clone needs to flush the TLBs since there are no ASIDs in
X86 TLBs, this change moves the flush into the clone system call.

Change-Id: Ic069ca02994436b36246403f9faef80c3aede55a
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
M src/arch/x86/utility.cc
M src/sim/syscall_emul.hh
2 files changed, 4 insertions(+), 6 deletions(-)



diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b53ca..cb99d4e 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -213,9 +213,8 @@
 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
-    // This function assumes no side effects other than TLB invalidation
-    // need to be considered while copying state. That will likely not be
-    // true in the future.
+    // This function assumes no side effects need to be considered
+    // while copying state.
     for (int i = 0; i < NUM_MISCREGS; ++i) {
         if (!isValidMiscReg(i))
              continue;
@@ -226,9 +225,6 @@
     // The TSC has to be updated with side-effects if the CPUs in a
     // CPU switch have different frequencies.
     dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
-
-    dest->getITBPtr()->flushAll();
-    dest->getDTBPtr()->flushAll();
 }

 void
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 7efd7c7..2911c7f 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1339,6 +1339,8 @@
         ctc->setMiscRegNoEffect(TheISA::MISCREG_FS_BASE, tlsPtr);
         ctc->setMiscRegNoEffect(TheISA::MISCREG_FS_EFF_BASE, tlsPtr);
     }
+    ctc->getITBPtr()->flushAll();
+    ctc->getDTBPtr()->flushAll();
 #endif

     if (newStack)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic069ca02994436b36246403f9faef80c3aede55a
Gerrit-Change-Number: 4000
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
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