Sean Wilson has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3923 )
Change subject: cpu: Refactor some Event subclasses to lambdas
......................................................................
cpu: Refactor some Event subclasses to lambdas
Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3923
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
10 files changed, 30 insertions(+), 138 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 78b25ca..6f76b8c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -248,7 +248,9 @@
if (FullSystem) {
if (params()->profile)
- profileEvent = new ProfileEvent(this, params()->profile);
+ profileEvent = new EventFunctionWrapper(
+ [this]{ processProfileEvent(); },
+ name());
}
tracer = params()->tracer;
@@ -658,21 +660,15 @@
}
}
-
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
- : cpu(_cpu), interval(_interval)
-{ }
-
void
-BaseCPU::ProfileEvent::process()
+BaseCPU::processProfileEvent()
{
- ThreadID size = cpu->threadContexts.size();
- for (ThreadID i = 0; i < size; ++i) {
- ThreadContext *tc = cpu->threadContexts[i];
- tc->profileSample();
- }
+ ThreadID size = threadContexts.size();
- cpu->schedule(this, curTick() + interval);
+ for (ThreadID i = 0; i < size; ++i)
+ threadContexts[i]->profileSample();
+
+ schedule(profileEvent, curTick() + params()->profile);
}
void
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b49f302..79a4bf1 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -248,17 +248,8 @@
return FullSystem &&
interrupts[tc->threadId()]->checkInterrupts(tc);
}
- class ProfileEvent : public Event
- {
- private:
- BaseCPU *cpu;
- Tick interval;
-
- public:
- ProfileEvent(BaseCPU *cpu, Tick interval);
- void process();
- };
- ProfileEvent *profileEvent;
+ void processProfileEvent();
+ EventFunctionWrapper * profileEvent;
protected:
std::vector<ThreadContext *> threadContexts;
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 3b70c53..bf26120 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -321,7 +321,8 @@
LSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
bool isLoad_, PacketDataPtr data_, uint64_t *res_) :
LSQRequest(port_, inst_, isLoad_, data_, res_),
- translationEvent(*this),
+ translationEvent([this]{ sendNextFragmentToTranslation(); },
+ "translationEvent"),
numFragments(0),
numInTranslationFragments(0),
numTranslatedFragments(0),
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 1a90948..d4973f5 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -377,20 +377,7 @@
{
protected:
/** Event to step between translations */
- class TranslationEvent : public Event
- {
- protected:
- SplitDataRequest &owner;
-
- public:
- TranslationEvent(SplitDataRequest &owner_)
- : owner(owner_) { }
-
- void process()
- { owner.sendNextFragmentToTranslation(); }
- };
-
- TranslationEvent translationEvent;
+ EventFunctionWrapper translationEvent;
protected:
/** Number of fragments this request is split into */
unsigned int numFragments;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 5977f94..f508a37 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -101,21 +101,6 @@
typedef O3ThreadState<Impl> Thread;
- /** Event class used to schedule a squash due to a trap (fault or
- * interrupt) to happen on a specific cycle.
- */
- class TrapEvent : public Event {
- private:
- DefaultCommit<Impl> *commit;
- ThreadID tid;
-
- public:
- TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
-
- void process();
- const char *description() const;
- };
-
/** Overall commit status. Used to determine if the CPU can deschedule
* itself due to a lack of activity.
*/
@@ -157,6 +142,9 @@
/** To probe when an instruction is squashed */
ProbePointArg<DynInstPtr> *ppSquash;
+ /** Mark the thread as processing a trap. */
+ void processTrapEvent(ThreadID tid);
+
public:
/** Construct a DefaultCommit with the given parameters. */
DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index aba2696..bf5ee8a 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -71,26 +71,12 @@
using namespace std;
template <class Impl>
-DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
- ThreadID _tid)
- : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
-{
-}
-
-template <class Impl>
void
-DefaultCommit<Impl>::TrapEvent::process()
+DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
{
// This will get reset by commit if it was switched out at the
// time of this event processing.
- commit->trapSquash[tid] = true;
-}
-
-template <class Impl>
-const char *
-DefaultCommit<Impl>::TrapEvent::description() const
-{
- return "Trap";
+ trapSquash[tid] = true;
}
template <class Impl>
@@ -537,7 +523,9 @@
{
DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
- TrapEvent *trap = new TrapEvent(this, tid);
+ EventFunctionWrapper *trap = new EventFunctionWrapper(
+ [this, tid]{ processTrapEvent(tid); },
+ "Trap", true, Event::CPU_Tick_Pri);
Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
cpu->syscallRetryLatency : trapLatency;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c249d90..09790f4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -137,31 +137,12 @@
}
template <class Impl>
-FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
- : Event(CPU_Tick_Pri), cpu(c)
-{
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::TickEvent::process()
-{
- cpu->tick();
-}
-
-template <class Impl>
-const char *
-FullO3CPU<Impl>::TickEvent::description() const
-{
- return "FullO3CPU tick";
-}
-
-template <class Impl>
FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
: BaseO3CPU(params),
itb(params->itb),
dtb(params->dtb),
- tickEvent(this),
+ tickEvent([this]{ tick(); }, "FullO3CPU tick",
+ false, Event::CPU_Tick_Pri),
#ifndef NDEBUG
instcount(0),
#endif
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d78d1b9..28ccd15 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -199,24 +199,8 @@
virtual bool isSnooping() const { return true; }
};
- class TickEvent : public Event
- {
- private:
- /** Pointer to the CPU. */
- FullO3CPU<Impl> *cpu;
-
- public:
- /** Constructs a tick event. */
- TickEvent(FullO3CPU<Impl> *c);
-
- /** Processes a tick event, calling tick() on the CPU. */
- void process();
- /** Returns the description of the tick event. */
- const char *description() const;
- };
-
/** The tick event used for scheduling CPU ticks. */
- TickEvent tickEvent;
+ EventFunctionWrapper tickEvent;
/** Schedule tick event, regardless of its current state. */
void scheduleTickEvent(Cycles delay)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6c31f1d..c47686a 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -64,24 +64,6 @@
using namespace std;
using namespace TheISA;
-AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
- : Event(CPU_Tick_Pri), cpu(c)
-{
-}
-
-
-void
-AtomicSimpleCPU::TickEvent::process()
-{
- cpu->tick();
-}
-
-const char *
-AtomicSimpleCPU::TickEvent::description() const
-{
- return "AtomicSimpleCPU tick";
-}
-
void
AtomicSimpleCPU::init()
{
@@ -94,7 +76,10 @@
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
- : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
+ : BaseSimpleCPU(p),
+ tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
+ false, Event::CPU_Tick_Pri),
+ width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
icachePort(name() + ".icache_port", this),
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index cdc1890..c9dd954 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -60,16 +60,7 @@
private:
- struct TickEvent : public Event
- {
- AtomicSimpleCPU *cpu;
-
- TickEvent(AtomicSimpleCPU *c);
- void process();
- const char *description() const;
- };
-
- TickEvent tickEvent;
+ EventFunctionWrapper tickEvent;
const int width;
bool locked;
--
To view, visit https://gem5-review.googlesource.com/3923
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Gerrit-Change-Number: 3923
Gerrit-PatchSet: 5
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Sean Wilson <spwils...@wisc.edu>
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