Sean Wilson has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3929 )
Change subject: arm: Refactor some Event subclasses to lambdas
......................................................................
arm: Refactor some Event subclasses to lambdas
Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3929
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
4 files changed, 17 insertions(+), 32 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 126431f..d2ec1d7 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -87,7 +87,9 @@
cpuBpr[x] = GICC_BPR_MINIMUM;
// Initialize cpu highest int
cpuHighestInt[x] = SPURIOUS_INT;
- postIntEvent[x] = new PostIntEvent(*this, x);
+ postIntEvent[x] =
+ new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
+ "Post Interrupt to CPU");
}
DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n",
cpuEnabled[0],
cpuEnabled[1]);
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 60d9ae3..58d8434 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -353,21 +353,7 @@
*/
void postDelayedInt(uint32_t cpu);
- /** Event definition to post interrupt to CPU after a delay
- */
- class PostIntEvent : public Event
- {
- private:
- Pl390 &parent;
- uint32_t cpu;
- public:
- PostIntEvent(Pl390 &_parent, uint32_t _cpu)
- : parent(_parent), cpu(_cpu)
- { }
- void process() { parent.postDelayedInt(cpu); }
- const char *description() const { return "Post Interrupt to CPU"; }
- };
- PostIntEvent *postIntEvent[CPU_MAX];
+ EventFunctionWrapper *postIntEvent[CPU_MAX];
int pendingDelayedInterrupts;
public:
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 6744ad5..cc8ad77 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -53,7 +53,9 @@
maintInt(p->ppint)
{
for (int x = 0; x < VGIC_CPU_MAX; x++) {
- postVIntEvent[x] = new PostVIntEvent(x, p->platform);
+ postVIntEvent[x] = new EventFunctionWrapper(
+ [this, x]{ processPostVIntEvent(x); },
+ "Post VInterrupt to CPU");
maintIntPosted[x] = false;
vIntPosted[x] = false;
}
@@ -369,6 +371,13 @@
}
void
+VGic::processPostVIntEvent(uint32_t cpu)
+{
+ platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
+}
+
+
+void
VGic::postMaintInt(uint32_t cpu)
{
DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu);
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index e9bc29c..40e42d4 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -104,22 +104,10 @@
static const uint32_t LR_PENDING = 1;
static const uint32_t LR_ACTIVE = 2;
- /** Event definition to post interrupt to CPU after a delay
- */
- class PostVIntEvent : public Event
- {
- private:
- uint32_t cpu;
- Platform *platform;
- public:
- PostVIntEvent( uint32_t c, Platform* p)
- : cpu(c), platform(p)
- { }
- void process() { platform->intrctrl->post(cpu,
ArmISA::INT_VIRT_IRQ, 0);}
- const char *description() const { return "Post VInterrupt to CPU";
}
- };
+ /** Post interrupt to CPU */
+ void processPostVIntEvent(uint32_t cpu);
- PostVIntEvent *postVIntEvent[VGIC_CPU_MAX];
+ EventFunctionWrapper *postVIntEvent[VGIC_CPU_MAX];
bool maintIntPosted[VGIC_CPU_MAX];
bool vIntPosted[VGIC_CPU_MAX];
--
To view, visit https://gem5-review.googlesource.com/3929
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Gerrit-Change-Number: 3929
Gerrit-PatchSet: 6
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Sean Wilson <spwils...@wisc.edu>
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