Hi All, I am trying to replace our GPU model's vector register implementation with the one recently release by ARM: https://gem5.googlesource.com/public/gem5/+/0747a432d25ade2c197ca6393270e12606419872, and I noticed an issue I didn't catch when I previously reviewed the patch.
From the code, it seems that views of a vector register will break if we try to mix VecElem types across views. What I mean is, if we have a vector register file where each vector register is 64 lanes of uint32_t, trying to do an operation that views a vector register with lanes of uint16_t will only update the first half of the vector register with respect to an operation that views the vector register as uint32_t. Was that the intention? If so, how did you envision people handling operations of various sizes on the vector registers (i.e., updating only the lower 16b of a 32b lane)? I am thinking I will need to add support for some partial lane views, because our GPU instructions can do 16b operations that only update the lower bits of a 32b lane, but that has to be done across all lanes. -Tony _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
