Sean Wilson has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3980 )
Change subject: x86: Add stats to X86 TLB
......................................................................
x86: Add stats to X86 TLB
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
---
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
2 files changed, 47 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 191e91a..e954c9c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -332,7 +332,20 @@
DPRINTF(TLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
+ if (mode == Read) {
+ rdAccesses++;
+ } else {
+ wrAccesses++;
+ }
if (!entry) {
+ DPRINTF(TLB, "Handling a TLB miss for "
+ "address %#x at pc %#x.\n",
+ vaddr, tc->instAddr());
+ if (mode == Read) {
+ rdMisses++;
+ } else {
+ wrMisses++;
+ }
if (FullSystem) {
Fault fault = walker->start(tc, translation, req,
mode);
if (timing || fault != NoFault) {
@@ -343,10 +356,6 @@
entry = lookup(vaddr);
assert(entry);
} else {
- DPRINTF(TLB, "Handling a TLB miss for "
- "address %#x at pc %#x.\n",
- vaddr, tc->instAddr());
-
Process *p = tc->getProcessPtr();
TlbEntry newEntry;
bool success = p->pTable->lookup(vaddr, newEntry);
@@ -445,6 +454,29 @@
}
void
+TLB::regStats()
+{
+ using namespace Stats;
+
+ rdAccesses
+ .name(name() + ".rdAccesses")
+ .desc("TLB accesses on read requests");
+
+ wrAccesses
+ .name(name() + ".wrAccesses")
+ .desc("TLB accesses on write requests");
+
+ rdMisses
+ .name(name() + ".rdMisses")
+ .desc("TLB misses on read requests");
+
+ wrMisses
+ .name(name() + ".wrMisses")
+ .desc("TLB misses on write requests");
+
+}
+
+void
TLB::serialize(CheckpointOut &cp) const
{
// Only store the entries in use.
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a134ad4..09cd6ed 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,12 @@
TlbEntryTrie trie;
uint64_t lruSeq;
+ // Statistics
+ Stats::Scalar rdAccesses;
+ Stats::Scalar wrAccesses;
+ Stats::Scalar rdMisses;
+ Stats::Scalar wrMisses;
+
Fault translateInt(RequestPtr req, ThreadContext *tc);
Fault translate(RequestPtr req, ThreadContext *tc,
@@ -142,6 +148,11 @@
TlbEntry * insert(Addr vpn, TlbEntry &entry);
+ /*
+ * Function to register Stats
+ */
+ void regStats();
+
// Checkpointing
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
--
To view, visit https://gem5-review.googlesource.com/3980
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Gerrit-Change-Number: 3980
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Sean Wilson <[email protected]>
Gerrit-Reviewer: Swapnil Haria <[email protected]>
Gerrit-CC: Anthony Gutierrez <[email protected]>
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