Hi, In GEM5-TLM, there are two separate examples for master_port and slave_port. I am thinking to combine, so that in the same simulation we have both the master_port as well as slave_port in the TLM world. When looking into this, I realized we have this sim_control, to which I can either bind a master transactor or slave transactor. So do you think to have both master and slave ports I need to define a new transactor, which has both master and slave functionalities ?
The motivation for this is to support an accelerator or device which is a slave to the system, so the CPU can issue requests to it, but if it wants to read to write directly from memory it should also have a master port (Assuming memory is in GEM5-world). Regards Yasir _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
