Yes, that's a bug. Can you give these patches a try? https://gem5-review.googlesource.com/4580 https://gem5-review.googlesource.com/4581
Gabe On Thu, Aug 24, 2017 at 8:22 AM, Lebeane, Michael <[email protected]> wrote: > Hello all, > > Some of us AMD folks have noticed a weird issue concerning the rdcr > micro-op and x86 on O3 CPU. I occasionally trigger the following assertion > when running applications: > > gem5.opt: clangGCN3_X86/build/X86/arch/x86/isa.cc:133: MiscReg > X86ISA::ISA::readMiscRegNoEffect(int) const: Assertion > `isValidMiscReg(miscReg)' failed. > > I believe what is happening is that my application contains an > unimplemented control register read that is executed on a mispeculated > path. The logic appears to just assert whenever an unimplemented control > register is touched, regardless of when/where that happens. > > Does anyone with more familiarity with X86 and the O3 model agree that the > above behavior is possible? If so, what would be the correct way to fix > it? I suspect that the instruction should be marked as unimplemented and > should generate a fault on commit. > > Thanks! > Michael LeBeane > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
