Matthias Hille has uploaded this change for review. (
https://gem5-review.googlesource.com/4620
Change subject: cpu-o3: fix data pkt initialization for split load
......................................................................
cpu-o3: fix data pkt initialization for split load
When a split load hits a memory region where IPRs are mapped, the
Writebackevent which is scheduled for that was carrying a data packet
that was not correctly initialized which caused an assertion to fire
when the Writeback event is processed.
Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f
Signed-off-by: Matthias Hille <[email protected]>
Reported-by: Matthias Hille <[email protected]>
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9d88530..b8e8955 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -610,8 +610,8 @@
Cycles delay(0);
PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
+ data_pkt->dataStatic(load_inst->memData);
if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
- data_pkt->dataStatic(load_inst->memData);
delay = TheISA::handleIprRead(thread, data_pkt);
} else {
assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f
Gerrit-Change-Number: 4620
Gerrit-PatchSet: 1
Gerrit-Owner: Matthias Hille <[email protected]>
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