Hi Gabe, The MIDR register would be an obvious way to detect whether you're running in gem5 or not. This used have a gem5-specific implementer value, but was changed to ARM around the time when ARMv8 was added to gem5. However, assigning an undocumented value here is forbidden by the architecture spec, so we shouldn't do it.
One possibility would be to infer what you are running on from the device tree. We usually include 'gem5,armv8' in the CPU compatibility string and should probably do something similar for the platform. Something that would make m5ops more useful on ARM would be a thin kernel driver that exposes the memory-mapped m5op interface as a /dev node. The presence of this device would indicate m5op support and it could then be mapped into the application's memory space. This would actually solve the discovery problem when using m5ops since the base address is platform dependant. Cheers, Andreas On 25/08/2017 07:53, Gabe Black wrote:
Hello folks. We're planning to add checkpointing instructions to some of the software we're running on gem5 and want to be able to run the same software on real hardware. On x86 it's fairly easy to detect because the CPUID instruction returns strings which fairly clearly say that your running on gem5. On ARM, the CPUID registers seem to have more realistic values which don't indicate gem5. I see that the MIDR register has an "implementer" field which currently defaults to 0x41, meaning ARM. Would there be adverse affects from changing that to something else which means "gem5"? For instance, would the kernel do something differently because it doesn't think it's on the same type of CPU? Is there some other recommended method of detecting in software whether you're running under gem5 or not? Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
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