B.A. Zeeb has uploaded this change for review. (
https://gem5-review.googlesource.com/4861
Change subject: arch-x86: fix CondInst decoding for MOV to Control Registers
......................................................................
arch-x86: fix CondInst decoding for MOV to Control Registers
MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).
This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .
Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 8b87568..f0698ce 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -361,7 +361,7 @@
// no prefix
0x0: decode OPCODE_OP_BOTTOM3 {
0x0: CondInst::MOV(
- {{isValidMiscReg(MISCREG_CR(MODRM_RM))}},Rd,Cd);
+ {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Rd,Cd);
0x1: MOV(Rd,Dd);
0x2: CondInst::MOV(
{{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Cd,Rd);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Gerrit-Change-Number: 4861
Gerrit-PatchSet: 1
Gerrit-Owner: B.A. Zeeb <[email protected]>
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