Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/5541
Change subject: arch-arm: Corrected encoding for T32 HVC instruction
......................................................................
arch-arm: Corrected encoding for T32 HVC instruction
This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Chuan Zhu <chuan....@arm.com>
---
M src/arch/arm/isa/formats/branch.isa
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/isa/formats/branch.isa
b/src/arch/arm/isa/formats/branch.isa
index 513506d..df85b08 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010, 2012-2013 ARM Limited
+// Copyright (c) 2010,2012-2013,2017 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -247,7 +247,7 @@
}
}
}
- case 0xfe:
+ case 0x7e:
{
uint32_t imm16 = (bits(machInst, 19, 16) << 12) |
(bits(machInst, 11, 0) << 0);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Gerrit-Change-Number: 5541
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
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