Swapnil Haria has uploaded this change for review. (
https://gem5-review.googlesource.com/5582
Change subject: Adding basic config files
......................................................................
Adding basic config files
Change-Id: Iaec4f82890df2f65b694e42adf0ff7e45596debf
---
A configs/simple_fs/caches.py
A configs/simple_fs/run-cpu-fs.py
A configs/system/caches.py
A configs/system/cpu.py
A configs/system/fs_tools.py
A configs/system/run-cpu-fs.py
A configs/system/system.py
7 files changed, 1,331 insertions(+), 0 deletions(-)
diff --git a/configs/simple_fs/caches.py b/configs/simple_fs/caches.py
new file mode 100644
index 0000000..3fe42ed
--- /dev/null
+++ b/configs/simple_fs/caches.py
@@ -0,0 +1,245 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script. It uses the SimpleOpts wrapper to set up command
+line options from each individual class.
+"""
+
+from m5.objects import Cache, L2XBar, SubSystem
+from m5.params import AddrRange, AllMemory, MemorySize
+from m5.util.convert import toMemorySize
+
+import SimpleOpts
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+class L1Cache(Cache):
+ """Simple L1 Cache with default values"""
+
+ assoc = 2
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ mshrs = 4
+ tgts_per_mshr = 20
+
+ def __init__(self, options=None):
+ super(L1Cache, self).__init__()
+ pass
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU-side port
+ This must be defined in a subclass"""
+ raise NotImplementedError
+
+class L1ICache(L1Cache):
+ """Simple L1 instruction cache with default values"""
+
+ # Set the default size
+ size = '16kB'
+
+ SimpleOpts.add_option('--l1i_size',
+ help="L1 instruction cache size. Default: %s" %
size)
+
+ def __init__(self, opts=None):
+ super(L1ICache, self).__init__(opts)
+ if not opts or not opts.l1i_size:
+ return
+ self.size = opts.l1i_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU icache port"""
+ self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+ """Simple L1 data cache with default values"""
+
+ # Set the default size
+ size = '64kB'
+
+ SimpleOpts.add_option('--l1d_size',
+ help="L1 data cache size. Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L1DCache, self).__init__(opts)
+ if not opts or not opts.l1d_size:
+ return
+ self.size = opts.l1d_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU dcache port"""
+ self.cpu_side = cpu.dcache_port
+
+class L2Cache(Cache):
+ """Simple L2 Cache with default values"""
+
+ # Default parameters
+ size = '256kB'
+ assoc = 8
+ tag_latency = 20
+ data_latency = 20
+ response_latency = 20
+ mshrs = 20
+ tgts_per_mshr = 12
+
+ SimpleOpts.add_option('--l2_size', help="L2 cache size."
+ "Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L2Cache, self).__init__()
+ if not opts or not opts.l2_size:
+ return
+ self.size = opts.l2_size
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+
+class MMUCache(Cache):
+ # Default parameters
+ size = '8kB'
+ assoc = 4
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 20
+ tgts_per_mshr = 12
+ writeback_clean = True
+
+ SimpleOpts.add_option('--mmu_size', help="MMU cache size."
+ "Default: %s" % size)
+ def __init__(self, opts=None):
+ super(MMUCache, self).__init__()
+ if not opts or not opts.mmu_size:
+ return
+ self.size = opts.mmu_size
+
+ def connectCPU(self, cpu):
+ """Connect the CPU itb and dtb to the cache
+ Note: This creates a new crossbar
+ """
+ self.mmubus = L2XBar()
+ self.cpu_side = self.mmubus.master
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.slave = tlb.walker.port
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+class L3CacheBank(Cache):
+ """Simple L3 Cache bank with default values
+ This assumes that the L3 is made up of multiple banks. This cannot
+ be used as a standalone L3 cache.
+ """
+
+ # Default parameters
+ assoc = 32
+ tag_latency = 40
+ data_latency = 40
+ response_latency = 10
+ mshrs = 256
+ tgts_per_mshr = 12
+ clusivity = 'mostly_excl'
+
+ def __init__(self, size):
+ super(L3CacheBank, self).__init__()
+ self.size = size
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+
+
+class BankedL3Cache(SubSystem):
+ """An L3 cache that is made up of multiple L3CacheBanks
+ This class creates mulitple banks that add up to a total L3 cache
+ size. The current interleaving works on a cache line granularity
+ with no upper-order xor bits.
+ Note: We cannot use the default prefetchers with a banked cache.
+ """
+
+ SimpleOpts.add_option('--l3_size', default = '4MB',
+ help="L3 cache size. Default: 4MB")
+ SimpleOpts.add_option('--l3_banks', default = 4, type = 'int',
+ help="L3 cache banks. Default: 4")
+
+ def __init__(self, opts):
+ super(BankedL3Cache, self).__init__()
+
+ total_size = toMemorySize(opts.l3_size)
+
+ if total_size % opts.l3_banks:
+ m5.fatal("The L3 size must be divisible by number of banks")
+
+ bank_size = MemorySize(opts.l3_size) / opts.l3_banks
+ self.banks = [L3CacheBank(size = bank_size)
+ for i in range(opts.l3_banks)]
+ ranges = self._getInterleaveRanges(AllMemory, opts.l3_banks, 7, 0)
+ for i, bank in enumerate(self.banks):
+ bank.addr_ranges = ranges[i]
+
+ def connectCPUSideBus(self, bus):
+ for bank in self.banks:
+ bank.connectCPUSideBus(bus)
+
+ def connectMemSideBus(self, bus):
+ for bank in self.banks:
+ bank.connectMemSideBus(bus)
+
+ def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
+ from math import log
+ bits = int(log(num, 2))
+ if 2**bits != num:
+ m5.fatal("Non-power of two number of memory ranges")
+
+ intlv_bits = bits
+ ranges = [
+ AddrRange(start=rng.start,
+ end=rng.end,
+ intlvHighBit = intlv_low_bit + intlv_bits - 1,
+ xorHighBit = xor_low_bit + intlv_bits - 1,
+ intlvBits = intlv_bits,
+ intlvMatch = i)
+ for i in range(num)
+ ]
+
+ return ranges
diff --git a/configs/simple_fs/run-cpu-fs.py
b/configs/simple_fs/run-cpu-fs.py
new file mode 100644
index 0000000..b06f23a
--- /dev/null
+++ b/configs/simple_fs/run-cpu-fs.py
@@ -0,0 +1,181 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a single CPU and a two-level cache system.
+This script takes a single parameter which specifies a binary to execute.
+If none is provided it executes 'hello' by default (mostly used for
testing)
+
+See Part 1, Chapter 3: Adding cache to the configuration script in the
+learning_gem5 book for more information about this script.
+This file exports options for the L1 I/D and L2 cache sizes.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+ also needs to be updated. For now, email Jason
<[email protected]>
+
+"""
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+# Add the common scripts to our path
+m5.util.addToPath('../common')
+m5.util.addToPath('../system')
+
+# import the caches which we made
+from caches import *
+
+# import the SimpleOpts module
+import SimpleOpts
+
+from enum import Enum
+
+from system import MySystem
+
+import os
+
+SimpleOpts.add_option("--script", default='',
+ help="Script to execute in the simulated system")
+
+SimpleOpts.add_option("--tlb_size", type='int',
+ default=128, help ="cpu TLB size. Default: 16")
+
+SimpleOpts.add_option("--mmu_cache", type='int',
+ default=0, help ="mmu-cache for CPU. Default:0")
+
+# Set the usage message to display
+SimpleOpts.set_usage("usage: %prog [options]")
+
+# Finalize the arguments and grab the opts so we can pass it on to our
objects
+(opts, args) = SimpleOpts.parse_args()
+
+# Cause error if there are too many arguments
+if len(args) != 0:
+ m5.panic("Incorrect number of arguments!")
+
+# create the system we are going to simulate
+system = MySystem(opts)
+
+#Size the cpu data TLB
+system.timingCpu[0].dtb.size = opts.tlb_size
+
+# Use CPU mmucache
+#system.cpu[0].mmucache.mmubus.slave = system.graph_engine.tlb.walker.port
+
+# For workitems to work correctly
+# This will cause the simulator to exit simulation when the first work
+# item is reached and when the first work item is finished.
+system.work_begin_exit_count = 1
+system.work_end_exit_count = 1
+
+# Read in the script file passed in via an option.
+# This file gets read and executed by the simulated system after boot.
+# Note: The disk image needs to be configured to do this.
+system.readfile = opts.script
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = True, system = system)
+
+if system.getHostParallel():
+ # Required for running kvm on multiple host cores.
+ # Uses gem5's parallel event queue feature
+ # Note: The simulator is quite picky about this number!
+ root.sim_quantum = int(1e9) # 1 ms
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+# TODO handle via ioremap in real driver
+#system.cpu.workload[0].map(0x10000000, 0x200000000, 4096)
+
+print "Beginning simulation!"
+
+# While there is still something to do in the guest keep executing.
+# This is needed since we exit for the ROI begin/end
+foundROI = False
+warmup = False
+end_tick = 0
+start_tick = 0
+file = open(os.path.join(m5.options.outdir, 'running.txt'), 'w+')
+# Timeout if ROI not reached! value used is 3x synthetic-s24's startup time
+exit_event = m5.simulate(10436253276578452)
+while exit_event.getCause() != "m5_exit instruction encountered":
+
+ print "Exited because", exit_event.getCause()
+ simulate_limit = -1
+ # If the user pressed ctrl-c on the host, then we really should exit
+ if exit_event.getCause() == "user interrupt received":
+ print "User interrupt. Exiting"
+ break
+ elif exit_event.getCause() == "exiting with last active thread
context":
+ if not foundROI:
+ print "Program exited prematurely"
+ import sys
+ sys.exit()
+ else:
+ break
+
+ if exit_event.getCause() == "work started count reach":
+ print "ROI found"
+ print "Warmup begins!"
+ system.mem_mode = 'timing'
+ m5.memWriteback(system)
+ m5.memInvalidate(system)
+ system.switchCpus(system.cpu, system.timingCpu)
+ m5.stats.reset()
+ foundROI = True
+ warmup = True
+ simulate_limit = 100000000000
+ elif exit_event.getCause() == "work items exit count reached":
+ os.remove(os.path.join(m5.options.outdir, 'running.txt'))
+ end_tick = m5.curTick()
+ break
+ # Got stuck in boot loop
+ elif exit_event.getCause() == "simulate() limit reached" and not
foundROI:
+ if start_tick == 0:
+ print "Boot timed out"
+ file =
open(os.path.join(m5.options.outdir, 'killed.txt'), 'w+')
+ break
+ elif exit_event.getCause() == "simulate() limit reached" and warmup:
+ print "Warmup Complete!"
+ print "Actual Simulation Begins"
+ start_tick = m5.curTick()
+ m5.stats.reset()
+ warmup = False
+ simulate_limit = 5000000000000
+ elif exit_event.getCause() == "simulate() limit reached":
+ os.remove(os.path.join(m5.options.outdir, 'running.txt'))
+ end_tick = m5.curTick()
+ break
+
+ print "Continuing after", exit_event.getCause()
+ exit_event = m5.simulate(simulate_limit)
+
+print "ROI:", end_tick - start_tick, "ticks"
diff --git a/configs/system/caches.py b/configs/system/caches.py
new file mode 100644
index 0000000..3fe42ed
--- /dev/null
+++ b/configs/system/caches.py
@@ -0,0 +1,245 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script. It uses the SimpleOpts wrapper to set up command
+line options from each individual class.
+"""
+
+from m5.objects import Cache, L2XBar, SubSystem
+from m5.params import AddrRange, AllMemory, MemorySize
+from m5.util.convert import toMemorySize
+
+import SimpleOpts
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+class L1Cache(Cache):
+ """Simple L1 Cache with default values"""
+
+ assoc = 2
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ mshrs = 4
+ tgts_per_mshr = 20
+
+ def __init__(self, options=None):
+ super(L1Cache, self).__init__()
+ pass
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU-side port
+ This must be defined in a subclass"""
+ raise NotImplementedError
+
+class L1ICache(L1Cache):
+ """Simple L1 instruction cache with default values"""
+
+ # Set the default size
+ size = '16kB'
+
+ SimpleOpts.add_option('--l1i_size',
+ help="L1 instruction cache size. Default: %s" %
size)
+
+ def __init__(self, opts=None):
+ super(L1ICache, self).__init__(opts)
+ if not opts or not opts.l1i_size:
+ return
+ self.size = opts.l1i_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU icache port"""
+ self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+ """Simple L1 data cache with default values"""
+
+ # Set the default size
+ size = '64kB'
+
+ SimpleOpts.add_option('--l1d_size',
+ help="L1 data cache size. Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L1DCache, self).__init__(opts)
+ if not opts or not opts.l1d_size:
+ return
+ self.size = opts.l1d_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU dcache port"""
+ self.cpu_side = cpu.dcache_port
+
+class L2Cache(Cache):
+ """Simple L2 Cache with default values"""
+
+ # Default parameters
+ size = '256kB'
+ assoc = 8
+ tag_latency = 20
+ data_latency = 20
+ response_latency = 20
+ mshrs = 20
+ tgts_per_mshr = 12
+
+ SimpleOpts.add_option('--l2_size', help="L2 cache size."
+ "Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L2Cache, self).__init__()
+ if not opts or not opts.l2_size:
+ return
+ self.size = opts.l2_size
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+
+class MMUCache(Cache):
+ # Default parameters
+ size = '8kB'
+ assoc = 4
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 20
+ tgts_per_mshr = 12
+ writeback_clean = True
+
+ SimpleOpts.add_option('--mmu_size', help="MMU cache size."
+ "Default: %s" % size)
+ def __init__(self, opts=None):
+ super(MMUCache, self).__init__()
+ if not opts or not opts.mmu_size:
+ return
+ self.size = opts.mmu_size
+
+ def connectCPU(self, cpu):
+ """Connect the CPU itb and dtb to the cache
+ Note: This creates a new crossbar
+ """
+ self.mmubus = L2XBar()
+ self.cpu_side = self.mmubus.master
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.slave = tlb.walker.port
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+class L3CacheBank(Cache):
+ """Simple L3 Cache bank with default values
+ This assumes that the L3 is made up of multiple banks. This cannot
+ be used as a standalone L3 cache.
+ """
+
+ # Default parameters
+ assoc = 32
+ tag_latency = 40
+ data_latency = 40
+ response_latency = 10
+ mshrs = 256
+ tgts_per_mshr = 12
+ clusivity = 'mostly_excl'
+
+ def __init__(self, size):
+ super(L3CacheBank, self).__init__()
+ self.size = size
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+
+
+class BankedL3Cache(SubSystem):
+ """An L3 cache that is made up of multiple L3CacheBanks
+ This class creates mulitple banks that add up to a total L3 cache
+ size. The current interleaving works on a cache line granularity
+ with no upper-order xor bits.
+ Note: We cannot use the default prefetchers with a banked cache.
+ """
+
+ SimpleOpts.add_option('--l3_size', default = '4MB',
+ help="L3 cache size. Default: 4MB")
+ SimpleOpts.add_option('--l3_banks', default = 4, type = 'int',
+ help="L3 cache banks. Default: 4")
+
+ def __init__(self, opts):
+ super(BankedL3Cache, self).__init__()
+
+ total_size = toMemorySize(opts.l3_size)
+
+ if total_size % opts.l3_banks:
+ m5.fatal("The L3 size must be divisible by number of banks")
+
+ bank_size = MemorySize(opts.l3_size) / opts.l3_banks
+ self.banks = [L3CacheBank(size = bank_size)
+ for i in range(opts.l3_banks)]
+ ranges = self._getInterleaveRanges(AllMemory, opts.l3_banks, 7, 0)
+ for i, bank in enumerate(self.banks):
+ bank.addr_ranges = ranges[i]
+
+ def connectCPUSideBus(self, bus):
+ for bank in self.banks:
+ bank.connectCPUSideBus(bus)
+
+ def connectMemSideBus(self, bus):
+ for bank in self.banks:
+ bank.connectMemSideBus(bus)
+
+ def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
+ from math import log
+ bits = int(log(num, 2))
+ if 2**bits != num:
+ m5.fatal("Non-power of two number of memory ranges")
+
+ intlv_bits = bits
+ ranges = [
+ AddrRange(start=rng.start,
+ end=rng.end,
+ intlvHighBit = intlv_low_bit + intlv_bits - 1,
+ xorHighBit = xor_low_bit + intlv_bits - 1,
+ intlvBits = intlv_bits,
+ intlvMatch = i)
+ for i in range(num)
+ ]
+
+ return ranges
diff --git a/configs/system/cpu.py b/configs/system/cpu.py
new file mode 100644
index 0000000..a0c9bf9
--- /dev/null
+++ b/configs/system/cpu.py
@@ -0,0 +1,50 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" Out-of order CPU with some defaults designed for high-performance
+This file contains a derived CPU from the O3 CPU that is designed to
+have lots of memory-level parallelism to push the memory system
+"""
+
+from m5.objects import DerivO3CPU
+from m5.objects import FUPool
+from m5.objects import IntALU, IntMultDiv, FP_ALU, FP_MultDiv, ReadPort
+from m5.objects import SIMD_Unit, WritePort, RdWrPort, IprPort
+
+class MemoryParallelismFUPool(FUPool):
+ FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+ SIMD_Unit(), WritePort(), RdWrPort(count = 8), IprPort() ]
+
+class HighPerformanceCPU(DerivO3CPU):
+
+ LQEntries = 64
+ SQEntries = 64
+
+ fuPool = MemoryParallelismFUPool()
+
diff --git a/configs/system/fs_tools.py b/configs/system/fs_tools.py
new file mode 100644
index 0000000..4b41df0
--- /dev/null
+++ b/configs/system/fs_tools.py
@@ -0,0 +1,48 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
+
+class CowDisk(IdeDisk):
+
+ def __init__(self, filename):
+ super(CowDisk, self).__init__()
+ self.driveID = 'master'
+ self.image = CowDiskImage(child=RawDiskImage(read_only=True),
+ read_only=False)
+ self.image.child.image_file = filename
+
+class RawDisk(IdeDisk):
+
+ def __init__(self, filename):
+ super(RawDisk, self).__init__()
+ self.driveID = 'master'
+ self.image = RawDiskImage(child=RawDiskImage(read_only=False),
+ read_only=False)
+ self.image.child.image_file = filename
diff --git a/configs/system/run-cpu-fs.py b/configs/system/run-cpu-fs.py
new file mode 100644
index 0000000..50238fd
--- /dev/null
+++ b/configs/system/run-cpu-fs.py
@@ -0,0 +1,169 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a single CPU and a two-level cache system.
+This script takes a single parameter which specifies a binary to execute.
+If none is provided it executes 'hello' by default (mostly used for
testing)
+
+See Part 1, Chapter 3: Adding cache to the configuration script in the
+learning_gem5 book for more information about this script.
+This file exports options for the L1 I/D and L2 cache sizes.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+ also needs to be updated. For now, email Jason
<[email protected]>
+
+"""
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+# Add the common scripts to our path
+m5.util.addToPath('../common')
+#m5.util.addToPath('../system')
+
+# import the caches which we made
+from caches import *
+
+# import the SimpleOpts module
+import SimpleOpts
+
+from enum import Enum
+
+from system import MySystem
+
+import os
+
+SimpleOpts.add_option("--script", default='',
+ help="Script to execute in the simulated system")
+
+# Set the usage message to display
+SimpleOpts.set_usage("usage: %prog [options]")
+
+# Finalize the arguments and grab the opts so we can pass it on to our
objects
+(opts, args) = SimpleOpts.parse_args()
+
+# Cause error if there are too many arguments
+if len(args) != 0:
+ m5.panic("Incorrect number of arguments!")
+
+# create the system we are going to simulate
+system = MySystem(opts)
+
+# For workitems to work correctly
+# This will cause the simulator to exit simulation when the first work
+# item is reached and when the first work item is finished.
+system.work_begin_exit_count = 1
+system.work_end_exit_count = 1
+
+# Read in the script file passed in via an option.
+# This file gets read and executed by the simulated system after boot.
+# Note: The disk image needs to be configured to do this.
+system.readfile = opts.script
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = True, system = system)
+
+if system.getHostParallel():
+ # Required for running kvm on multiple host cores.
+ # Uses gem5's parallel event queue feature
+ # Note: The simulator is quite picky about this number!
+ root.sim_quantum = int(1e9) # 1 ms
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+# TODO handle via ioremap in real driver
+#system.cpu.workload[0].map(0x10000000, 0x200000000, 4096)
+
+print "Beginning simulation!"
+
+# While there is still something to do in the guest keep executing.
+# This is needed since we exit for the ROI begin/end
+foundROI = False
+warmup = False
+end_tick = 0
+start_tick = 0
+file = open(os.path.join(m5.options.outdir, 'running.txt'), 'w+')
+# Timeout if ROI not reached! Number chosen randomly replace TODO
+exit_event = m5.simulate(10436253275200000)
+while exit_event.getCause() != "m5_exit instruction encountered":
+
+ print "Exited because", exit_event.getCause()
+ simulate_limit = 1
+ # If the user pressed ctrl-c on the host, then we really should exit
+ if exit_event.getCause() == "user interrupt received":
+ print "User interrupt. Exiting"
+ break
+ elif exit_event.getCause() == "exiting with last active thread
context":
+ if not foundROI:
+ print "Program exited prematurely"
+ import sys
+ sys.exit()
+ else:
+ break
+
+ if exit_event.getCause() == "work started count reach":
+ print "ROI found"
+ print "Warmup begins!"
+ system.mem_mode = 'timing'
+ m5.memWriteback(system)
+ m5.memInvalidate(system)
+ system.switchCpus(system.cpu, system.timingCpu)
+ m5.stats.reset()
+ foundROI = True
+ warmup = True
+ simulate_limit = 100000000000
+ elif exit_event.getCause() == "work items exit count reached":
+ os.remove(os.path.join(m5.options.outdir, 'running.txt'))
+ end_tick = m5.curTick()
+ break
+ # Got stuck in boot loop
+ elif exit_event.getCause() == "simulate() limit reached" and not
foundROI:
+ if start_tick == 0:
+ print "Boot timed out"
+ file =
open(os.path.join(m5.options.outdir, 'killed.txt'), 'w+')
+ break
+ elif exit_event.getCause() == "simulate() limit reached" and warmup:
+ print "Warmup Complete!"
+ print "Actual Simulation Begins"
+ start_tick = m5.curTick()
+ m5.stats.reset()
+ warmup = False
+ simulate_limit = 5000000000000
+ elif exit_event.getCause() == "simulate() limit reached":
+ os.remove(os.path.join(m5.options.outdir, 'running.txt'))
+ end_tick = m5.curTick()
+ break
+
+ print "Continuing after", exit_event.getCause()
+ exit_event = m5.simulate(simulate_limit)
+
+print "ROI:", end_tick - start_tick, "ticks"
diff --git a/configs/system/system.py b/configs/system/system.py
new file mode 100644
index 0000000..d781040
--- /dev/null
+++ b/configs/system/system.py
@@ -0,0 +1,393 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import m5
+from m5.objects import *
+from m5.util import convert
+from fs_tools import *
+from caches import *
+import os
+
+class MySystem(LinuxX86System):
+
+ SimpleOpts.add_option("--no_host_parallel", default=False,
+ action="store_true",
+ help="Do NOT run gem5 on multiple host threads (kvm only)")
+
+ SimpleOpts.add_option("--cpus", default=1, type="int",
+ help="Number of CPUs in the system")
+
+ SimpleOpts.add_option("--mem-size", default="16GB", type="string",
+ help="Memory in the system")
+
+ SimpleOpts.add_option("--second_disk",
+
default='/p/multifacet/users/swapnilh/disk_images/'+
+ 'linux-bigswap2.img',
+ help="The second disk image to mount (/dev/hdb)")
+
+ def __init__(self, opts, no_kvm=False):
+ super(MySystem, self).__init__()
+ self._opts = opts
+ self._no_kvm = no_kvm
+
+ self._host_parallel = not self._opts.no_host_parallel
+
+ # Set up the clock domain and the voltage domain
+ self.clk_domain = SrcClockDomain()
+ self.clk_domain.clock = '3GHz'
+ self.clk_domain.voltage_domain = VoltageDomain()
+ print "System memory:", opts.mem_size
+ self.mem_ranges = [AddrRange('100MB'), # For kernel
+ AddrRange(0xC0000000, size=0x100000), # For I/0
+ AddrRange(Addr('4GB'), size = opts.mem_size) #
data
+ ]
+ self.mmap_using_noreserve = True
+ # Create the main memory bus
+ # This connects to main memory
+ self.membus = SystemXBar(width = 64) # 64-byte width
+ self.membus.badaddr_responder = BadAddr()
+ self.membus.default = Self.badaddr_responder.pio
+
+ # Set up the system port for functional access from the simulator
+ self.system_port = self.membus.slave
+
+ self.initFS(self.membus, self._opts.cpus)
+
+ # Replace these paths with the path to your disk images.
+ # The first disk is the root disk. The second could be used for
swap
+ # or anything else.
+ # Todo: Move to backed up location
+ filepath =
os.getenv('M5_PATH', '/nobackup/swapnilh/pm-studies/gem5/')
+ imagepath = os.path.join(filepath, 'ubuntu.img')
+ swap_imagepath = os.path.join(filepath, opts.second_disk)
+ self.setDiskImages(imagepath, swap_imagepath)
+
+ # Change this path to point to the kernel you want to use
+ self.kernel = os.path.join(filepath, 'vmlinux-4.14-rc6')
+
+ # Options specified on the kernel command line
+ boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
+ 'root=/dev/hda1']
+ self.boot_osflags = ' '.join(boot_options)
+
+ # Create the CPUs for our system.
+ self.createCPU()
+
+ # Create the cache heirarchy for the system.
+ self.createCacheHierarchy()
+
+ # Set up the interrupt controllers for the system (x86 specific)
+ self.setupInterrupts()
+
+ self.createMemoryControllersDDR3()
+
+ if self._host_parallel:
+ # To get the KVM CPUs to run on different host CPUs
+ # Specify a different event queue for each CPU
+ for i,cpu in enumerate(self.cpu):
+ for obj in cpu.descendants():
+ obj.eventq_index = 0
+ cpu.eventq_index = i + 1
+
+ def getHostParallel(self):
+ return self._host_parallel
+
+ def totalInsts(self):
+ return sum([cpu.totalInsts() for cpu in self.cpu])
+
+ def createCPU(self):
+ if self._no_kvm:
+ self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
+ for i in range(self._opts.cpus)]
+ else:
+ # Note KVM needs a VM and atomic_noncaching
+ self.kvm_vm = KvmVM()
+ self.cpu = [X86KvmCPU(cpu_id = i)
+ for i in range(self._opts.cpus)]
+ self.mem_mode = 'atomic_noncaching'
+
+ self.atomicCpu = [TimingSimpleCPU(cpu_id = i,
+ switched_out = True)
+ for i in range(self._opts.cpus)]
+
+ self.timingCpu = [DerivO3CPU(cpu_id = i,
+ switched_out = True)
+ for i in range(self._opts.cpus)]
+
+ def switchCpus(self, old, new):
+ assert(new[0].switchedOut())
+ m5.switchCpus(self, zip(old, new))
+
+ def setDiskImages(self, img_path_1, img_path_2):
+ disk0 = CowDisk(img_path_1)
+ disk2 = CowDisk(img_path_2)
+ self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+ def createCacheHierarchy(self):
+ # Create an L3 cache (with crossbar)
+# self.l3bus = L2XBar(width = 64,
+# snoop_filter =
SnoopFilter(max_capacity='32MB'))
+
+ for cpu in self.cpu:
+ # Create a memory bus, a coherent crossbar, in this case
+ cpu.l2bus = L2XBar()
+
+ # Create an L1 instruction and data cache
+ cpu.icache = L1ICache(self._opts)
+ cpu.dcache = L1DCache(self._opts)
+ cpu.mmucache = MMUCache()
+
+ # Connect the instruction and data caches to the CPU
+ cpu.icache.connectCPU(cpu)
+ cpu.dcache.connectCPU(cpu)
+ cpu.mmucache.connectCPU(cpu)
+
+ # Hook the CPU ports up to the l2bus
+ cpu.icache.connectBus(cpu.l2bus)
+ cpu.dcache.connectBus(cpu.l2bus)
+ cpu.mmucache.connectBus(cpu.l2bus)
+
+ # Create an L2 cache and connect it to the l2bus
+ cpu.l2cache = L2Cache(self._opts)
+ cpu.l2cache.connectCPUSideBus(cpu.l2bus)
+
+ # Connect the L2 cache to the membus
+ cpu.l2cache.connectMemSideBus(self.membus)
+
+# self.l3cache = BankedL3Cache(self._opts)
+# self.l3cache.connectCPUSideBus(self.l3bus)
+
+ # Connect the L3 cache to the membus
+# self.l3cache.connectMemSideBus(self.membus)
+
+ def setupInterrupts(self):
+ for cpu in self.cpu:
+ # create the interrupt controller CPU and connect to the membus
+ cpu.createInterruptController()
+
+ # For x86 only, connect interrupts to the memory
+ # Note: these are directly connected to the memory bus and
+ # not cached
+ cpu.interrupts[0].pio = self.membus.master
+ cpu.interrupts[0].int_master = self.membus.slave
+ cpu.interrupts[0].int_slave = self.membus.master
+
+
+ def createMemoryControllersDDR3(self):
+ self._createMemoryControllers(2, DDR3_1600_8x8)
+
+ def _createMemoryControllers(self, num, cls):
+ kernel_controller = self._createKernelMemoryController(cls)
+
+ ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
+
+ self.mem_cntrls = [
+ cls(range = ranges[i],
+ port = self.membus.master,
+ channels = num)
+ for i in range(num)
+ ] + [kernel_controller]
+
+ def _createKernelMemoryController(self, cls):
+ return cls(range = self.mem_ranges[0],
+ port = self.membus.master,
+ channels = 1)
+
+ def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
+ from math import log
+ bits = int(log(num, 2))
+ if 2**bits != num:
+ m5.fatal("Non-power of two number of memory controllers")
+
+ intlv_bits = bits
+ ranges = [
+ AddrRange(start=rng.start,
+ end=rng.end,
+ intlvHighBit = intlv_low_bit + intlv_bits - 1,
+ xorHighBit = xor_low_bit + intlv_bits - 1,
+ intlvBits = intlv_bits,
+ intlvMatch = i)
+ for i in range(num)
+ ]
+
+ return ranges
+
+ def initFS(self, membus, cpus):
+ self.pc = Pc()
+
+ # Constants similar to x86_traits.hh
+ IO_address_space_base = 0x8000000000000000
+ pci_config_address_space_base = 0xc000000000000000
+ interrupts_address_space_base = 0xa000000000000000
+ APIC_range_size = 1 << 12;
+
+ # North Bridge
+ self.iobus = IOXBar()
+ self.bridge = Bridge(delay='50ns')
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = membus.master
+ # Allow the bridge to pass through:
+ # 1) kernel configured PCI device memory map address: address
range
+ # [0xC0000000, 0xFFFE0000). (The upper 64kB are reserved for
m5ops.)
+ # 2) the bridge to pass through the IO APIC (two pages, already
+ # contained in 1),
+ # 3) everything in the IO address range up to the local APIC, and
+ # 4) then the entire PCI address space and beyond.
+ self.bridge.ranges = \
+ [
+ AddrRange(0xC0000000, 0xFFFE0000),
+ AddrRange(IO_address_space_base,
+ interrupts_address_space_base - 1),
+ AddrRange(pci_config_address_space_base,
+ Addr.max)
+ ]
+
+ # Create a bridge from the IO bus to the memory bus to allow access
+ # to the local APIC (two pages)
+ self.apicbridge = Bridge(delay='50ns')
+ self.apicbridge.slave = self.iobus.master
+ self.apicbridge.master = membus.slave
+ self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
+ interrupts_address_space_base +
+ cpus * APIC_range_size
+ - 1)]
+
+ # connect the io bus
+ self.pc.attachIO(self.iobus)
+
+ # Add a tiny cache to the IO bus.
+ # This cache is required for the classic memory model for coherence
+ self.iocache = Cache(assoc=8,
+ tag_latency = 50,
+ data_latency = 50,
+ response_latency = 50,
+ mshrs = 20,
+ size = '1kB',
+ tgts_per_mshr = 12,
+ addr_ranges = self.mem_ranges)
+ self.iocache.cpu_side = self.iobus.master
+ self.iocache.mem_side = self.membus.slave
+
+ self.intrctrl = IntrControl()
+
+ ###############################################
+
+ # Add in a Bios information structure.
+ self.smbios_table.structures = [X86SMBiosBiosInformation()]
+
+ # Set up the Intel MP table
+ base_entries = []
+ ext_entries = []
+ for i in range(cpus):
+ bp = X86IntelMPProcessor(
+ local_apic_id = i,
+ local_apic_version = 0x14,
+ enable = True,
+ bootstrap = (i ==0))
+ base_entries.append(bp)
+ io_apic = X86IntelMPIOAPIC(
+ id = cpus,
+ version = 0x11,
+ enable = True,
+ address = 0xfec00000)
+ self.pc.south_bridge.io_apic.apic_id = io_apic.id
+ base_entries.append(io_apic)
+ pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
+ base_entries.append(pci_bus)
+ isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
+ base_entries.append(isa_bus)
+ connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+ subtractive_decode=True, parent_bus=0)
+ ext_entries.append(connect_busses)
+ pci_dev4_inta = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = 0 + (4 << 2),
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 16)
+ base_entries.append(pci_dev4_inta)
+ def assignISAInt(irq, apicPin):
+ assign_8259_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'ExtInt',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 0)
+ base_entries.append(assign_8259_to_apic)
+ assign_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = apicPin)
+ base_entries.append(assign_to_apic)
+ assignISAInt(0, 2)
+ assignISAInt(1, 1)
+ for i in range(3, 15):
+ assignISAInt(i, i)
+ self.intel_mp_table.base_entries = base_entries
+ self.intel_mp_table.ext_entries = ext_entries
+
+ entries = \
+ [
+ # Mark the first megabyte of memory as reserved
+ X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+ X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+ # Mark the rest of physical memory as available
+ X86E820Entry(addr = 0x100000,
+ size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+ range_type = 1),
+ ]
+ # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which
+ # force IO devices to be mapped to [0xC0000000, 0xFFFF0000).
Requests
+ # to this specific range can pass though bridge to iobus.
+ entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
+ size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
+ range_type=2))
+
+ # Reserve the last 32kB of the 32-bit address space for m5ops
+ entries.append(X86E820Entry(addr = 0xFFFF0000, size = '32kB',
+ range_type=2))
+
+ # Reserve 32kB of the 32-bit address space for accelerator
+ entries.append(X86E820Entry(addr = 0xFFFF8000, size = '32kB',
+ range_type=2))
+
+ # Add the rest of memory. This is where all the actual data is
+ entries.append(X86E820Entry(addr = self.mem_ranges[-1].start,
+ size='%dB' % (self.mem_ranges[-1].size()),
+ range_type=1))
+
+ self.e820_table.entries = entries
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaec4f82890df2f65b694e42adf0ff7e45596debf
Gerrit-Change-Number: 5582
Gerrit-PatchSet: 1
Gerrit-Owner: Swapnil Haria <[email protected]>
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