Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/5361 )
Change subject: arch-arm: Removing FlushPipe fault, using SquashAfter
......................................................................
arch-arm: Removing FlushPipe fault, using SquashAfter
This Patch is removing the FlushPipe ArmFault, which was used for
flushing the pipeline in favour of the general IsSquashAfter StaticInstr
flag. Using a fault was preventing tracers from tracing barriers like
ISB and from adding them to the instruction count
Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5361
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
5 files changed, 15 insertions(+), 46 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 740d71d..ef9d05a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2014, 2016 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -278,11 +278,6 @@
"SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat()
};
-template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = {
- // Some dummy values
- "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
- 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
-};
template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = {
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -1399,19 +1394,6 @@
}
void
-FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
- DPRINTF(Faults, "Invoking FlushPipe Fault\n");
-
- // Set the PC to the next instruction of the faulting instruction.
- // Net effect is simply squashing all instructions behind and
- // start refetching from the next instruction.
- PCState pc = tc->pcState();
- assert(inst);
- inst->advancePC(pc);
- tc->pcState(pc);
-}
-
-void
ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
if (!FullSystem)
@@ -1443,7 +1425,6 @@
template class ArmFaultVals<PCAlignmentFault>;
template class ArmFaultVals<SPAlignmentFault>;
template class ArmFaultVals<SystemError>;
-template class ArmFaultVals<FlushPipe>;
template class ArmFaultVals<ArmSev>;
template class AbortFault<PrefetchAbort>;
template class AbortFault<DataAbort>;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 8d72dee..de5061b 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -546,15 +546,6 @@
};
// A fault that flushes the pipe, excluding the faulting instructions
-class FlushPipe : public ArmFaultVals<FlushPipe>
-{
- public:
- FlushPipe() {}
- void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
-};
-
-// A fault that flushes the pipe, excluding the faulting instructions
class ArmSev : public ArmFaultVals<ArmSev>
{
public:
@@ -592,7 +583,6 @@
template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
-template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals;
template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index ab38e29..aa3d93d 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014,2016 ARM Limited
+ * Copyright (c) 2014,2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -190,6 +190,9 @@
flags[IsNonSpeculative] = true;
iss = _iss;
miscReg = _miscReg;
+
+ if (miscReg == MISCREG_DCCMVAC)
+ flags[IsSquashAfter] = true;
}
Fault
@@ -207,12 +210,9 @@
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, iss,
EC_TRAPPED_CP15_MCR_MRC);
- }
-
- if (miscReg == MISCREG_DCCMVAC)
- return std::make_shared<FlushPipe>();
- else
+ } else {
return NoFault;
+ }
}
std::string
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 4681d50..b42c9f9 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1070,12 +1070,11 @@
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
}
- fault = std::make_shared<FlushPipe>();
'''
isbIop = InstObjParams("isb", "Isb", "ImmOp",
{"code": isbCode,
"predicate_test": predicateTest},
- ['IsSerializeAfter'])
+ ['IsSerializeAfter', 'IsSquashAfter'])
header_output += ImmOpDeclare.subst(isbIop)
decoder_output += ImmOpConstructor.subst(isbIop)
exec_output += PredOpExecute.subst(isbIop)
@@ -1087,12 +1086,12 @@
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
}
- fault = std::make_shared<FlushPipe>();
'''
dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
{"code": dsbCode,
"predicate_test": predicateTest},
- ['IsMemBarrier', 'IsSerializeAfter'])
+ ['IsMemBarrier', 'IsSerializeAfter',
+ 'IsSquashAfter'])
header_output += ImmOpDeclare.subst(dsbIop)
decoder_output += ImmOpConstructor.subst(dsbIop)
exec_output += PredOpExecute.subst(dsbIop)
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index 08902ab..ac9f0a9 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -139,16 +139,15 @@
decoder_output += BasicConstructor64.subst(unknown64Iop)
exec_output += BasicExecute.subst(unknown64Iop)
- isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst",
- "fault = std::make_shared<FlushPipe>();",
- ['IsSerializeAfter'])
+ isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "",
+ ['IsSerializeAfter', 'IsSquashAfter'])
header_output += BasicDeclare.subst(isbIop)
decoder_output += BasicConstructor64.subst(isbIop)
exec_output += BasicExecute.subst(isbIop)
- dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst",
- "fault = std::make_shared<FlushPipe>();",
- ['IsMemBarrier', 'IsSerializeAfter'])
+ dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
+ ['IsMemBarrier', 'IsSerializeAfter',
+ 'IsSquashAfter'])
header_output += BasicDeclare.subst(dsbIop)
decoder_output += BasicConstructor64.subst(dsbIop)
exec_output += BasicExecute.subst(dsbIop)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff
Gerrit-Change-Number: 5361
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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