Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/5702
to review the following change.
Change subject: cpu: MinorCPU handling IsSquashAfter flag
......................................................................
cpu: MinorCPU handling IsSquashAfter flag
MinorCPU was not handling IsSquashAfter flagged instructions. The
behaviour was to force a branch (hence enforcing refetching) for
SerializeAfter instructions only. This has now been extended to
SquashAfter in order to correctly support ISB barrier instruction
behaviour.
Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/cpu/minor/execute.cc
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index a38a767..7b76ca2 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -219,13 +219,14 @@
const TheISA::PCState &pc_before = inst->pc;
TheISA::PCState target = thread->pcState();
- /* Force a branch for SerializeAfter instructions at the end of
micro-op
- * sequence when we're not suspended */
+ /* Force a branch for SerializeAfter/SquashAfter instructions
+ * at the end of micro-op sequence when we're not suspended */
bool force_branch = thread->status() != ThreadContext::Suspended &&
!inst->isFault() &&
inst->isLastOpInInst() &&
(inst->staticInst->isSerializeAfter() ||
- inst->staticInst->isIprAccess());
+ inst->staticInst->isSquashAfter() ||
+ inst->staticInst->isIprAccess());
DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
pc_before, target, (force_branch ? " (forcing)" : ""));
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Gerrit-Change-Number: 5702
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
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