Andreas Sandberg has uploaded a new patch set (#4) to the change originally
created by Anouk Van Laer. ( https://gem5-review.googlesource.com/3969 )
Change subject: pwr: Adds logic to enter power gating for the cpu model
......................................................................
pwr: Adds logic to enter power gating for the cpu model
If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.
Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/cpu.cc
M src/cpu/o3/cpu.cc
M src/cpu/simple/atomic.cc
M src/cpu/simple/timing.cc
7 files changed, 90 insertions(+), 8 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Gerrit-Change-Number: 3969
Gerrit-PatchSet: 4
Gerrit-Owner: Anouk Van Laer <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Anouk Van Laer <[email protected]>
Gerrit-CC: Jason Lowe-Power <[email protected]>
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