Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6026
Change subject: arch-riscv: Move compressed ops out of ISA
......................................................................
arch-riscv: Move compressed ops out of ISA
This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.
Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 47 insertions(+), 29 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index d058f85..39205a2 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,6 +2,7 @@
if env['TARGET_ISA'] == 'riscv':
Source('amo.cc')
+ Source('compressed.cc')
Source('mem.cc')
Source('standard.cc')
Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/compressed.cc
b/src/arch/riscv/insts/compressed.cc
new file mode 100644
index 0000000..8a8481e
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.cc
@@ -0,0 +1,21 @@
+#include "arch/riscv/insts/compressed.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+ registerName(_srcRegIdx[0]);
+ return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.hh
b/src/arch/riscv/insts/compressed.hh
new file mode 100644
index 0000000..7d7e693
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.hh
@@ -0,0 +1,24 @@
+#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
+#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for compressed operations that work only on registers
+ */
+class CompRegOp : public RiscvStaticInst
+{
+ protected:
+ using RiscvStaticInst::RiscvStaticInst;
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/compressed.isa
b/src/arch/riscv/isa/formats/compressed.isa
index 1fd2319..91b6672 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -28,35 +28,6 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
-
-output header {{
- /**
- * Base class for compressed operations that work only on registers
- */
- class CompRegOp : public RiscvStaticInst
- {
- protected:
- /// Constructor
- CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string
- CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
- {
- std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]);
- return ss.str();
- }
-}};
-
def format CROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index f4662da..9f3d99f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -43,6 +43,7 @@
#include <vector>
#include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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