Hello Gabe Black,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/6022
to look at the new patch set (#4).
Change subject: arch-riscv: Move standard ops out of ISA
......................................................................
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/standard.cc
A src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 192 insertions(+), 148 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Gerrit-Change-Number: 6022
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
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