Hi, I am trying to implement another part of the cpuid instruction, namely leaf 4, which returns deterministic cache parameters of the system (size, associativity, etc). However, I'm a bit stumped as to how I can actually access this information. There doesn't seem to be any way to get a pointer to a Cache object from the CPU or the System. The most I've been able to find is getting a handle to the master port for either the icache or the dcache, but even then there's no way to get a handle to the owner of the corresponding slave port. It seems that the only bird's eye view of the system is available in Python. So if this is all true, then would the best way to implement this to be precomputing all the register outputs in python and setting them appropriately in the CPU objects as the caches are instantiated?
Thanks, Sam -- Thanks, Sam Xi Harvard University Computer Science, Ph.D. Candidate http://www.samxi.org _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
