Hello,
I think there is a bug in src/cpu/BaseCPU.py, which results in the failure
to add the appropriate 'isa' information in 'switch_cpus' parameters.
Because of this, when '-r' option is added to the commandline (restoring
from checkpoint), the isa section of the 'switch_cpus' parameters in the
config.ini file (under output directory, e.g. m5out) becomes empty so it
prevents from restoring gem5 from checkpoint.
I have checked the same file of the older repository, and found the recent
BaseCPU.py creates isa instance with 'empty' list while previous one did
with 'isa_class.'
Here is my suggested update.
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index d174f274a..18d9a6d3e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -167,24 +167,24 @@ class BaseCPU(MemObject):
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
interrupts = VectorParam.SparcInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.SparcISA([], "ISA instance")
+ isa = VectorParam.SparcISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
interrupts = VectorParam.AlphaInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.AlphaISA([], "ISA instance")
+ isa = VectorParam.AlphaISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'x86':
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
- isa = VectorParam.X86ISA([], "ISA instance")
+ isa = VectorParam.X86ISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'mips':
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
interrupts = VectorParam.MipsInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.MipsISA([], "ISA instance")
+ isa = VectorParam.MipsISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'arm':
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
@@ -192,20 +192,20 @@ class BaseCPU(MemObject):
dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
interrupts = VectorParam.ArmInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.ArmISA([], "ISA instance")
+ isa = VectorParam.ArmISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
interrupts = VectorParam.PowerInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.PowerISA([], "ISA instance")
+ isa = VectorParam.PowerISA([ default_isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'riscv':
dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
interrupts = VectorParam.RiscvInterrupts(
[], "Interrupt Controller")
- isa = VectorParam.RiscvISA([], "ISA instance")
+ isa = VectorParam.RiscvISA([ default_isa_class() ], "ISA instance")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
Thanks.
Regards,
Dong Wan Kim
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
